DSPIC33FJ128MC510-I/PT Microchip Technology, DSPIC33FJ128MC510-I/PT Datasheet - Page 21

• Manufacturer Part Number: DSPIC33FJ128MC510-I/PT
• Description: IC DSPIC MCU/DSP 128K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC510-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

54. Module: ECAN
55. Module: I
© 2010 Microchip Technology Inc.
The WAKIF bit in the CxINTF register cannot be
cleared by software instruction after the device is
interrupted from Sleep by activity on the CAN bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN event interrupt
occurs due to the WAKIF flag. Attempts to clear
the flag in the Interrupt Service Routine may not
clear the flag. The WAKIF bit being set will not
cause
execution.
Work around
Although the WAKIF bit does not clear, the device
Sleep and ECAN Wake function continue to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and Wake events.
Affected Silicon Revisions
When the I
after the ACKSTAT bit is set when receiving a
NACK from the slave, it may be cleared by the
reception of a Start or Stop bit.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
repetitive
2
2
C module is operating in Master mode,
C
A4
A4
X
X
Interrupt
Service
Routine
56. Module: PWM
57. Module: PWM
Under certain conditions, devices in the motor
control family have a glitch in the PWMxL signal.
The glitch is a brief high pulse during the low
portion of the duty cycle. This error occurs when
the module is configured in Single-Shot mode
(PTMOD<1:0> = 01) with complementary output.
It also occurs when resuming from a Fault
condition
(PTMOD<1:0) = 00) with complementary output.
Work around
None.
Affected Silicon Revisions
If a Fault is cleared by user software during
Latched mode, while the current PWM cycle
remains active, any additional faults that arrive
before the end of the current PWM cycle will not be
detected. The PWM outputs will return to the non-
Fault state at the end of that cycle and remain
there, even if the fault is currently active. No
interrupt will be sent to the interrupt controller.
Work around
While in the Latched mode of operation, do not
attempt to clear faults during the same cycle in
which they arrive.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
A4
A4
X
X
in
Free-Running
DS80447D-page 21
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