DSPIC33FJ128MC510-I/PT Microchip Technology, DSPIC33FJ128MC510-I/PT Datasheet - Page 9

• Manufacturer Part Number: DSPIC33FJ128MC510-I/PT
• Description: IC DSPIC MCU/DSP 128K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC510-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4. Module: CPU
© 2010 Microchip Technology Inc.
The EXCH instruction does not execute correctly.
Work around
If
recommended fix is to replace:
with:
If using the MPLAB C Compiler for dsPIC
(formerly known as the MPLAB C30 C Compiler),
specify the compiler option, -merrata=exch
(Project>Build Options>Projects>MPLAB
C30>Use Alternate Settings)
Affected Silicon Revisions
A2
X
writing
A3
X
EXCH Wsource, Wdestination
PUSH Wdestination
MOV Wsource, Wdestination
POP Wsource
source
A4
X
code
in
assembly,
®
DSCs
the
5. Module: CPU
The DISI instruction will not disable interrupts
when a DISI instruction is executed in the same
instruction
decrements to zero. For example, when user code
executes a DISI #7, interrupts for 7 + 1 cycles
(7 + the DISI instruction itself) are disabled. In
that case, the DISI instruction uses a counter that
counts down from 7 to 0. The counter is loaded
with 7 at the end of the DISI instruction.
If the user code executes another DISI on the
instruction cycle where the DISI counter has
become zero, the new DISI count is loaded; but,
the DISI state machine does not properly re-
engage and continue to disable interrupts. At this
point, all interrupts are enabled. The next time the
user code executes a DISI instruction, the feature
will act normally and block interrupts.
In summary, it is only when a DISI execution is
coincident with the current DISI count = 0, that the
issue occurs. Executing a DISI instruction before
the DISI counter reaches zero will not produce
this error – the DISI counter is loaded with the
new value, and interrupts remain disabled until the
counter becomes zero.
Work around
When multiple DISI instructions are executed in
the source code, make sure that subsequent DISI
instructions have at least one instruction cycle
between the time that the DISI counter
decrements to zero and the next DISI instruction.
Alternatively, make sure that subsequent DISI
instructions are called before the DISI counter
decrements to zero.
Affected Silicon Revisions
A2
X
A3
X
cycle
A4
X
that
the
DS80447D-page 9
DISI
counter