DSPIC33FJ128MC510-I/PT Microchip Technology, DSPIC33FJ128MC510-I/PT Datasheet - Page 3

• Manufacturer Part Number: DSPIC33FJ128MC510-I/PT
• Description: IC DSPIC MCU/DSP 128K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC510-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Doze Mode
Controller
Regulator
Device ID
Oscillator
Compare
Interrupt
Register
Module
Internal
Voltage
Output
UART
UART
UART
UART
UART
UART
ECAN
UART
JTAG
DMA
DMA
SPI
I
I
I
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Programming
Match Mode
Slave Mode
Slave Mode
Sleep Mode
High-Speed
High-Speed
Doze Mode
Idle Modes
Auto-Baud
Auto-Baud
Sleep and
SILICON ISSUE SUMMARY (CONTINUED)
Idle Mode
Accuracy
Compare
Overflow
SDI1 Pin
Feature
Receive
Mode
Mode
Flash
FRC
Dual
—
—
—
—
—
—
Number
Item
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
If a clock failure occurs when the device is in Idle mode, the
An MCLR wake-up from Sleep mode does not wait for the on-chip
The auto-baud feature measures baud rate inaccurately for
The address error trap, stack error trap, math error trap, and
DMA error trap will not wake-up a device from Doze mode.
JTAG programming does not work.
With the parity option enabled, a parity error may occur if the
Baud Rate Generator (BRG) contains an odd value.
The Receive Buffer Overrun Error Status bit may get set before
the UART FIFO has overflowed.
UART receptions may be corrupted if the BRG is set up for 4x
mode.
The UTXISEL0 bit is always read back as zero.
The auto-baud feature may not calculate the correct baud rate
when the BRG is set up for 4x mode.
With the auto-baud feature selected, the Sync Break character
(0x55) may be loaded into the FIFO as data.
A write collision does not prevent the transmit register from
being written.
The ACKSTAT bit reflects the received ACK/NACK status for
master transmissions, but not for slave transmissions.
The D_A Status bit is not set on a slave write to the transmit
register.
oscillator failure trap does not vector to the Trap Service
Routine (TSR).
voltage regulator to power-up.
The C1RXOVF2 and C2RXOVF2 registers always read back
as 0x0000.
Internal FRC accuracy parameters are not within the published
data sheet specifications.
SPI1 functionality for pin 34 (U1RX/SDI1/RF2) is erroneously
enabled by the SPI2 module.
certain baud rate and clock speed combinations.
The content of the Device ID register changes from the factory
programmed value.
DMA data transfers that are active in Single-Shot mode while
the device is in Sleep or Idle mode may result in more data
transfers than expected.
A DMA error trap may not be generated when the device is in
Doze mode.
In Dual Compare Match mode, the OCx output is not reset
when the OCxR and OCxRS registers are loaded with values
that have a difference of 1.
Issue Summary
DS80447D-page 3
Revisions
A2 A3 A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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X
X
(1)