DSPIC33FJ128MC510-I/PT Microchip Technology, DSPIC33FJ128MC510-I/PT Datasheet - Page 24

• Manufacturer Part Number: DSPIC33FJ128MC510-I/PT
• Description: IC DSPIC MCU/DSP 128K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC510-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

63. Module: SPI
64. Module: UART
65. Module: QEI
DS80447D-page 24
Writing to the SPIxBUF register as soon as the
TBF bit is cleared will cause the SPI module to
ignore the written data. Applications which use SPI
with DMA will not be affected by this erratum.
Work around
After the TBF bit is cleared, wait for a minimum
duration of one SPI Clock before writing to the
SPIxBUF register.
Alternately, do one of the following:
a)
b)
c)
d)
Affected Silicon Revisions
The UART module will not generate consecutive
break characters. Trying to perform a back-to-back
Break character transmission will cause the UART
module to transmit the dummy character that is
used to generate the first Break character instead
of transmitting the second Break character. Break
characters are generated correctly if they are
followed by a non-Break character transmission.
Work around
None.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt should
be generated after an input pulse on the QEA
input. This interrupt is not generated in the affected
silicon.
Work around
None.
Affected Silicon Revisions
A2
A2
A2
X
X
X
Poll the RBF bit and wait for it to get set
before writing to the SPIxBUF register
Poll the SPI Interrupt flag and wait for it to
get set before writing to the SPIxBUF
register
Use an SPI Interrupt Service Routine (ISR)
Use DMA
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
66. Module: QEI
67. Module: I/O
68. Module: SPI
When the TQCS and TQGATE bits in the
QEIxCON register are set, the POSCNT counter
should not increment but erroneously does; and if
allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSCNT
while
Accumulation mode, initialize MAXCNT = 0.
Affected Silicon Revisions
While the device is being programmed via the
PGECx/PGEDx pin pair, the device pin with SDO1
functionality may start toggling.
Work around
None.
Affected Silicon Revisions
Regardless of the Slave setting for the Frame
delay bit (FRMDLY = 0 or FRMDLY = 1), the Slave
always acts as if the sync pulse precedes the first
SPI data bit (FRMDLY = 0). The SPI will not
function as described if Slave FRMDLY = 1.
Work around
None.
Affected Silicon Revisions
A2
A2
A2
X
X
X
running
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
the
© 2010 Microchip Technology Inc.
QEI
in
Timer
Gated