AT91SAM7L128-CU Atmel, AT91SAM7L128-CU Datasheet
AT91SAM7L128-CU
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AT91SAM7L128-CU Summary of contents
Page 1
... In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane – 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane – Single Cycle Access MHz in Worst Case Conditions – 128-bit Read Access – ...
Page 2
... Embedded 1.8V Regulator, Drawing for the Core with Programmable Output Voltage – Single Supply 1.8V - 3.6V • Fully Static Operation MHz at 85°C, Worst Case Conditions • Available in a 128-lead LQFP Green and a 144-ball LFBGA Green Package AT91SAM7L128/64 Preliminary 2 ® Infrared Modulation/Demodulation ® Two-wire EEPROMs and I ...
Page 3
... The AT91SAM7L128/64 are low power members of Atmel’s Smart ARM Microcontroller family based on the 32-bit ARM7 • AT91SAM7L128 features a 128 Kbyte high-speed Flash and a total of 6 Kbytes SRAM. • AT91SAM7L64 features a 64 Kbyte high-speed Flash and a total of 6 Kbytes SRAM. They also embed a large set of peripherals, including a Segment LCD Controller and a complete set of system functions minimizing the number of external components ...
Page 4
... Block Diagram Figure 2-1. AT91SAM7L128/64 Block Diagram TDI TDO TMS TCK JTAGSEL TST FIQ IRQ0-IRQ1 PCK0-PCK2 CLKIN PLL PLLRC XIN OSC XOUT 32k RCOSC VDDIO1 BOD POR VDDIO1 NRST NRSTB FWUP VDDIO1 DRXD DTXD SEG00-SEG39 COM0-COM9 RXD0 TXD0 SCK0 RTS0 CTS0 ...
Page 5
... Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select JTAGSEL JTAG Selection Flash and NVM Configuration Bits Erase ERASE Command 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Active Voltage Type Level Reference Comments Power Power Power Power Power Power Power ...
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... Timer Counter I/O Line B PWM0 - PWM3 PWM Channels MISO Master In Slave Out MOSI Master Out Slave In SPCK SPI Serial Clock NPCS0 SPI Peripheral Chip Select 0 NPCS1-NPCS3 SPI Peripheral Chip Select AT91SAM7L128/64 Preliminary 6 Active Voltage Type Level Reference Comments Reset/Test I/O Low VDDIO1 ...
Page 7
... Programming Ready PGMNVALID Data Direction PGMNOE Programming Read PGMCK Programming Clock PGMNCMD Programming Command COM[9:0] Common Terminals SEG[39:0] Segment Terminals 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Active Type Level Reference Comments Two-Wire Interface I/O I/O Analog-to-Digital Converter Input VDDCORE Input Analog VDDCORE ...
Page 8
... Package and Pinout The AT91SAM7L128/64 is available in: • 128-lead LQFP package with a 0.5 mm lead-pitch • 144-ball LFBGA package with a 0.8 mm pitch. The part is also available in die delivery. 4.1 128-lead LQFP Package Outline Figure 4-1 A detailed mechanical description is given in the Mechanical Characteristics section of the prod- uct datasheet ...
Page 9
... PA18 55 24 PA19 56 25 PA20 57 26 PA21 58 27 PA22 59 28 VDDCORE 60 29 PA23 61 30 PA24 62 31 PA25 63 32 VDDIO2 64 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary VDDLCD 65 VDD3V6 66 CAPM2 67 CAPP2 68 CAPM1 69 CAPP1 70 VDDINLCD 71 GND 72 PB0 73 PB1 74 PB2 75 PB3 76 PB4 77 PB5 78 PB6 79 PB7 ...
Page 10
... LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the Mechanical Characteristics section of the prod- uct datasheet. Figure 4-2. AT91SAM7L128/64 Preliminary 10 shows the orientation of the 144-ball LFBGA package. 144-ball LFBGA Package Outline (Top View Ball A1 6257A–ATARM–20-Feb-08 ...
Page 11
... FWUP F5 C6 TDI F6 C7 PC22/PGMD11 F7 C8 PC19/PGMD8 F8 C9 PC16/PGMD5 F9 C10 PC9/PGMM2 F10 C11 PC10/PGMM3 F11 C12 PC8/PGMM1 F12 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Signal Name Pin Signal Name PA6 G1 VDD3V6 PA5 G2 PA17 PA7 G3 PA16 NC G4 PA15 PC26/PGMD15 G5 GND PC25/PGMD14 G6 GND PC21/PGMD11 G7 ...
Page 12
... Power Supplies The AT91SAM7L128/64 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDOUT pin the output of the voltage regulator. Output voltage can be programmed from 1.55V to 1.80V by steps of 100 mV. • ...
Page 13
... When entering this mode, all PIO pins keep their previous states, they are reinitialized as inputs with pull-ups at wake-up. The AT91SAM7L128/64 can be awakened from this mode through the FWUP pin, an event on WUP0-15 pins RTC alarm or brownout event. Current consumption is 3.5 µA typical without the LCD controller running. ...
Page 14
... The fast restart circuitry, as shown in up signal to the power management controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded 2 MHz Fast RC oscillator, switches the master clock on this 2 MHz clock and reenables the processor clock disabled. AT91SAM7L128/64 Preliminary 14 SLCK FWUPEN ...
Page 15
... Voltage Regulator The AT91SAM7L128/64 embeds a voltage regulator that is managed by the supply controller. This internal regulator is only intended to supply the internal core of AT91SAM7L128/64. It fea- tures three different operating modes: • In normal mode, the voltage regulator consumes less than 30 µA static current and draws output current. • ...
Page 16
... For example, two capacitors can be used in parallel, 100 nF NPO and 4.7 µF X7R. 5.6 LCD Power Supply The AT91SAM7L128/64 embeds an on-chip LCD power supply comprising a regulated charge pump and an adjustable voltage regulator. The regulated charge pump output delivers 3.6V as long as its input is supplied between 1.8V and 3 ...
Page 17
... If the charge pump is not needed, the user can apply an external voltage. See Figure 5-5. Please note that in this topology, switching time enhancement buffers are not available. (Refer Section 10.13 ”Segment LCD 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary The LCD Regulator is Externally Supplied VDDIO2 VDDLCD ...
Page 18
... Typical Powering Schematics The AT91SAM7L128/64 supports a 1.8V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. ics to be used. Figure 5-6. AT91SAM7L128/64 Preliminary 18 3.3V System Single Power Supply Schematic VDDIO2 VDDLCD VDD3V6 VDDINLCD Main Supply (1.8V-3.6V) ...
Page 19
... Test Pin The TST pin is used for manufacturing test or fast programming mode of the AT91SAM7L128/64 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. ...
Page 20
... The PIO lines PC5 to PC8 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 2 mA. Each I/O is designed to achieve very small leakage. However, the total current drawn by all the I/O lines cannot exceed 150 mA. AT91SAM7L128/64 Preliminary 20 6257A–ATARM–20-Feb-08 ...
Page 21
... Remap Command – Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors – Peripheral protection against write and/or user access • Enhanced Embedded Flash Controller 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary ® high-performance 32-bit instruction set 21 ...
Page 22
... Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements AT91SAM7L128/64 Preliminary 22 wait states 6257A–ATARM–20-Feb-08 ...
Page 23
... Memories • 128 Kbytes of Flash Memory (AT91SAM7L128) – Single plane – One bank of 512 pages of 256 bytes – Fast access time, 15 MHz single-cycle access in Worst Case conditions – Page programming time: 4.6 ms, including page auto-erase – Page programming without auto-erase: 2.3 ms – ...
Page 24
... Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF AT91SAM7L128/64 Preliminary 24 Internal Memory Mapping 0x0000 0000 Boot Memory (1) 1 MBytes Flash before Remap SRAM after Remap 0x000F FFFF 0x0010 0000 Internal Flash ...
Page 25
... After remap, the 4-Kbyte Core SRAM also becomes available at address 0x0. The user can see the 6 Kbytes of SRAM contiguously at address 0x002F F000. 8.1.1.2 Internal ROM The AT91SAM7L128/64 embeds an Internal ROM. The ROM is always mapped at address 0x0040 0000. The ROM contains the FFPI and SAM-BA program. ROM size is 12 Kbytes. 8.1.1.3 Internal Flash • ...
Page 26
... Embedded Flash 8.1.2.1 Flash Overview • The Flash of the AT91SAM7L128 is organized in 512 pages (single plane) of 256 bytes. • The Flash of the AT91SAM7L64 is organized in 256 pages (single plane) of 256 bytes. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. 8.1.2.2 Flash Power Supply The Flash is supplied by VDDCORE through a power switch controlled by the Supply Controller ...
Page 27
... Flash organization, thus making the software generic. 8.1.2.4 Lock Regions The AT91SAM7L128 Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7L128 contains 16 lock regions and each lock region contains 32 pages of 256 bytes. Each lock region has a size of 8 Kbytes ...
Page 28
... The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST and CLKIN are tied high while FWUP is tied low. • The Flash of the AT91SAM7L128 is organized in 512 pages of 256 bytes (single plane). • The Flash of the AT91SAM7L64 is organized in 256 pages of 256 bytes (single plane). ...
Page 29
... The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. ping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Figure 9-1 on page Figure 8-1 on page 24 30. shows the map- ...
Page 30
... XIN Xtal 32 kHz Oscillator XOUT Embedded 32 kHz RC Oscillator Backup Power Supply core_nreset NRST FSTT0 - FSTT15 Embedded 2 MHz RC Oscillator FCIN SLCK PLLRC AT91SAM7L128/64 Preliminary 30 VDDIO1 vr_on vr_mode vr_ok supply_on Supply Controller lcd_mode lcd_out bod_on brown_out LCD Power Supply lcd_nreset rtc_on lcd_eof SLCK ...
Page 31
... Both monitor VDDIO1. The zero-power power-on reset circuit is always active. It provides an internal reset signal to the AT91SAM7L128/64 for power-on and power-off operations and ensures a proper reset for the Supply Controller. The brownout detection circuit is disabled by default and can be enabled by software. It monitors VDDIO1 ...
Page 32
... The unused oscillator is disabled so that power consumption is optimized. The 2 MHz Fast RC oscillator is the default selected clock (MAINCK) which is used at start-up . The user can select an external clock (CLKIN) through software. The PLL needs an external RC filter and starts very short time (inferior to 1 ms). AT91SAM7L128/64 Preliminary 32 6257A–ATARM–20-Feb-08 ...
Page 33
... The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. The LCD Controller clock is SCLK. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Clock Generator Block Diagram Clock Generator CLKIN Embedded ...
Page 34
... General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt 9.7 Debug Unit • Comprises: – One two-pin UART – One Interface for the Debug Communication Channel (DCC) support AT91SAM7L128/64 Preliminary 34 Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK /1,/2,/4, ...
Page 35
... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x2733 0740 (VERSION 0) for AT91SAM7L128 – Chip ID is 0x2733 0540 (VERSION 0) for AT91SAM7L64 9.8 Period Interval Timer • ...
Page 36
... EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in 10.2 Peripheral Identifiers The AT91SAM7L128/64 embeds a wide range of peripherals. Identifiers of the AT91SAM7L128/64. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID ...
Page 37
... Peripheral Multiplexing on PIO Lines The AT91SAM7L128/64 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. PIO Controller A, B and C control respectively 26, 24 and 30 lines. Each line can be assigned to one of two peripheral functions Table 10-2 on page 38 multiplexed on the PIO Controller A, B and C. The two columns “ ...
Page 38
... PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 AT91SAM7L128/64 Preliminary 38 Peripheral B Extra Function COM0 COM1 COM2 COM3 COM4 COM5 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 ...
Page 39
... RTS1 PB16 RTS0 PB17 DTR1 PB18 PWM0 PB19 PWM1 PB20 PWM2 PB21 PWM3 PB22 NPCS1 PB23 PCK0 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary PIO Controller B Peripheral B Extra Function SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 ...
Page 40
... PC25 TXD1 PC26 RTS0 PC27 NPCS2 PC28 SCK1 PC29 RTS1 Notes: 1. Wake-Up source in Backup mode (managed by the SUPC). 2. Fast Start-Up source in Wait mode (managed by the PMC). AT91SAM7L128/64 Preliminary 40 PIO Controller C Peripheral B Extra Functions PWM2 PGMEN0/WKUP0 TIOA2 PGMEN1/WKUP1 TIOB2 PGMEN2/WKUP2 TCLK1 PGMNCMD/WKUP3 ...
Page 41
... Optional break generation and detection – over-sampling receiver frequency – Hardware handshaking RTS - CTS – Modem Signals Management DTR-DSR-DCD-RI on USART1 – Receiver time-out and transmitter timeguard 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary peripherals Sensors between clock and data ® and 3-wire EEPROMs ...
Page 42
... Four channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs AT91SAM7L128/64 Preliminary 42 Table 10-5 Timer Counter Clock Assignment Clock ...
Page 43
... Power-save mode display • Software-selectable low-power waveform capability • Flexible frame frequency selection • Segment and common pins, not needed for driving the display, can be used as ordinary I/O pins • Switching time enhancement internal buffers 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary enabled channels 43 ...
Page 44
... AT91SAM7L128/64 Preliminary 44 6257A–ATARM–20-Feb-08 ...
Page 45
... The main features of the ARM7tDMI processor are: • ARM7TDMI Based on ARMv4T Architecture • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • Three-Stage Pipeline Architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 45 ...
Page 46
... At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention stack pointer. AT91SAM7L128/64 Preliminary 46 6257A–ATARM–20-Feb-08 ...
Page 47
... R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers that interrupt processing can begin with- out having to save these registers. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary ARM7TDMI ARM Modes and Registers Layout Supervisor Mode Abort Mode ...
Page 48
... Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). AT91SAM7L128/64 Preliminary 48 supports five types of exception and a privileged processing mode for each type. 6257A–ATARM–20-Feb-08 ...
Page 49
... Exception-generating instruction In Thumb mode, eight general-purpose registers R7, are available that are the same physical registers when executing ARM instructions. Some Thumb instructions also 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Operation Move ...
Page 50
... TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH AT91SAM7L128/64 Preliminary 50 gives the Thumb instruction mnemonic list. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right ...
Page 51
... Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 12.2 Block Diagram Figure 12-1. Debug and Test Block Diagram PDC 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary ICE/JTAG Boundary TAP TAP ICE ARM7TDMI DBGU ...
Page 52
... Application Examples 12.3.1 Debug Environment Figure 12-2 standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example AT91SAM7L128/64 Preliminary 52 shows a complete debug environment example. The ICE/JTAG interface is used for ICE/JTAG Interface ICE/JTAG Connector RS232 ...
Page 53
... NRST TST TCK TDI TDO TMS JTAGSEL DRXD DTXD 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary shows a test environment example. Test vectors are sent and interpreted by the Test Adaptor JTAG Interface ICE/JTAG Chip n Connector AT91SAM7Lxx AT91SAM7Lxx-based Application Board In Test Debug and Test Pin List ...
Page 54
... AT91SAM7L128 For further details on the Debug Unit, see the Debug Unit section. 12.5.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. AT91SAM7L128/64 Preliminary 54 AT91SAM7Lxx Chip IDs Chip ID 0x27330540 0x27330740 6257A–ATARM–20-Feb-08 ...
Page 55
... The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. For more information, please refer to BDSL files which are available for the SAM7L Series. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 55 ...
Page 56
... VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name AT91SAM7L64 AT91SAM7L128 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. Chip Name AT91SAM7L64 AT91SAM7L128 AT91SAM7L128/64 Preliminary PART NUMBER MANUFACTURER IDENTITY ...
Page 57
... The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Reset Controller vddcore_nreset NRST NRST ...
Page 58
... NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the ERSTL field is within RSTC_MR register, which is backed-up, it can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. AT91SAM7L128/64 Preliminary 58 Figure 13-2 shows the block diagram of the NRST Manager. ...
Page 59
... Figure 13-3. General Reset State SLCK MCK power_on_reset proc_nreset RSTTYP periph_nreset NRST (nrst_out) 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary shows how the General Reset affects the reset signals. Processor Startup = 2 cycles XXX EXTERNAL RESET LENGTH = 2 cycles Any Freq. 0x0 = General Reset XXX ...
Page 60
... NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 13-4. User Reset State SLCK Any MCK Freq. NRST Resynch. 2 cycles proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) AT91SAM7L128/64 Preliminary Resynch. 2 cycles XXX >= EXTERNAL RESET LENGTH Processor Startup = 2 cycles 0x4 = User Reset 6257A– ...
Page 61
... As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 61 ...
Page 62
... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. AT91SAM7L128/64 Preliminary 62 Any Resynch. ...
Page 63
... A User Reset cannot be entered. 13.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Any Freq. Processor Startup = 2 cycles Any XXX proc_nreset signal ...
Page 64
... URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 13-7. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM7L128/64 Preliminary 64 read RSTC_SR 2 cycle resynchronization 6257A–ATARM–20-Feb-08 Figure ...
Page 65
... Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset - 0x0000_0000 0x0000_0000 65 ...
Page 66
... PERRST: Peripheral Reset effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7L128/64 Preliminary KEY – ...
Page 67
... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – ...
Page 68
... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM7L128/64 Preliminary ...
Page 69
... Real Time Clock, Power Management Controller, Memory Controller, etc.). When a system interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading the status registers of the above system peripherals successively. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 32768 Divider Time Bus Interface ...
Page 70
... The user can not reset this flag reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: AT91SAM7L128/64 Preliminary 70 6257A–ATARM–20-Feb-08 ...
Page 71
... This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be pro- grammed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked ...
Page 72
... Figure 14-2. Update Sequence Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL Clear ACKUPD bit in RTC_SCCR Update Time andor Calendar values in Clear UPDTIM and/or UPDCAL bit in AT91SAM7L128/64 Preliminary 72 Begin bit(s) in RTC_CR Read RTC_SR No ACKUPD = 1 ? Yes RTC_TIMR/RTC_CALR RTC_CR End Polling or IRQ (if enabled) ...
Page 73
... Status Clear Command Register 0x20 Interrupt Enable Register 0x24 Interrupt Disable Register 0x28 Interrupt Mask Register 0x2C Valid Entry Register 0xFC Reserved Register 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Name Access RTC_CR Read-write RTC_MR Read-write RTC_TIMR Read-write RTC_CALR Read-write RTC_TIMALR Read-write ...
Page 74
... CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Week change (every Monday at time 00:00:00 Month change (every 01 of each month at time 00:00:00 Year change (every January 1 at time 00:00:00). AT91SAM7L128/64 Preliminary – ...
Page 75
... Access Type: Read-write 31 30 – – – – – – – – • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected 12-hour mode is selected. All non-significant bits read zero. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – – – – – – – – – – ...
Page 76
... The lowest four bits encode the units. The higher bits encode the tens. • HOUR: Current Hour The range that can be set (BCD) in 12-hour mode (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode AM PM. All non-significant bits read zero. AT91SAM7L128/64 Preliminary – – – ...
Page 77
... The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Day in Current Month The range that can be set (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary ...
Page 78
... This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled The hour-matching alarm is enabled. AT91SAM7L128/64 Preliminary – – ...
Page 79
... The month-matching alarm is disabled The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled The date-matching alarm is enabled. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – ...
Page 80
... No calendar event has occurred since the last clear least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. AT91SAM7L128/64 Preliminary – ...
Page 81
... Clears corresponding status flag in the Status Register (RTC_SR). • TIMCLR: Time Clear effect Clears corresponding status flag in the Status Register (RTC_SR). • CALCLR: Calendar Clear effect Clears corresponding status flag in the Status Register (RTC_SR). 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – – – 21 ...
Page 82
... SECEN: Second Event Interrupt Enable effect The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable effect The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable effect. • The selected calendar event interrupt is enabled. AT91SAM7L128/64 Preliminary – – – 21 ...
Page 83
... SECDIS: Second Event Interrupt Disable effect The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable effect The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable effect The selected calendar event interrupt is disabled. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – – – – ...
Page 84
... The second periodic interrupt is enabled. • TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled The selected calendar event interrupt is enabled. AT91SAM7L128/64 Preliminary – – ...
Page 85
... No invalid data has been detected in RTC_TIMALR (Time Alarm Register RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non-valid Calendar Alarm invalid data has been detected in RTC_CALALR (Calendar Alarm Register RTC_CALALR has contained invalid data since it was last programmed. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – – ...
Page 86
... AT91SAM7L128/64 Preliminary 86 6257A–ATARM–20-Feb-08 ...
Page 87
... Block Diagram Figure 15-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR set 0 PIT_SR PITS reset 0 ...
Page 88
... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. AT91SAM7L128/64 Preliminary 88 Figure 15-2 illustrates 6257A– ...
Page 89
... Figure 15-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler ...
Page 90
... Periodic Interval Timer (PIT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM7L128/64 Preliminary 90 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset ...
Page 91
... The Periodic Interval Timer is disabled when the PIV value is reached The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – – ...
Page 92
... PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. AT91SAM7L128/64 Preliminary – – – – ...
Page 93
... Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary PICNT 21 ...
Page 94
... Register Name: PIT_PIIR Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. AT91SAM7L128/64 Preliminary PICNT CPIV CPIV ...
Page 95
... Block Diagram Figure 16-1. Watchdog Timer Block Diagram write WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD ...
Page 96
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM7L128/64 Preliminary 96 6257A–ATARM–20-Feb-08 ...
Page 97
... Figure 16-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN ...
Page 98
... Watchdog Timer (WDT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM7L128/64 Preliminary 98 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6257A–ATARM–20-Feb-08 ...
Page 99
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary KEY – – – – ...
Page 100
... The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. AT91SAM7L128/64 Preliminary 100 ...
Page 101
... WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 101 ...
Page 102
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM7L128/64 Preliminary 102 – ...
Page 103
... Off Mode, current consumption reduced to below 1 microamp, exits on the assertion of the Force Wake Up pin (FWUP) • Backup Mode, current consumption reduced to a few microamps for Clock and SRAM retention, exits on multiple wake-up sources • Running Mode, reaches a 30-MIPS performance level 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 103 ...
Page 104
... Block Diagram Figure 17-1. Supply Controller Block Diagram Brownout Detector Zero-power Power-on Reset Embedded 32 kHz RC Oscillator XIN Xtal 32 kHz Oscillator 0 AT91SAM7L128/64 Preliminary 104 VDDIO1 vdd_on VDD_S W rt_on s upply_on fwup rtc_alarm rt_nres et bod_in s low_clock bod_on bod_thres hold s ram_on poweron_res et lcd_pump_on Supply ...
Page 105
... The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN. The input characteristics of the XIN pin are given in the product electrical characteristics section. In order to set the 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 105 ...
Page 106
... The Supply Controller also sets the status bit, FWUPS in the Supply Controller Status Register, SUPC_SR. This status bit is cleared as soon as SUPC_SR is read and indicates the first power up of the backup power supply. AT91SAM7L128/64 Preliminary 106 6257A–ATARM–20-Feb-08 ...
Page 107
... As soon as NRSTB is tied to GND, the supply controller is reset and all the system parts are powered off. When NRSTB is released, the system can start as described in Backup Power 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 30 Slow Clock Cycles = about 1ms Supply”. at least 1 Slow Clock Cycle Section 17.3.4.1 ”Raising the ...
Page 108
... Figure 17-4. NRSTB Reset when FWUP = 1 and NRSTB is Released Before FWUP = 0 NRSTB FWUP RC Oscillator output supply_on sram_on vr_standby vr_ok core_nreset AT91SAM7L128/64 Preliminary 108 30 Slow Clock Cycles = about 1ms 30 Slow Clock Cycles = about least 1 Slow Clock Cycle at least 1 Slow Clock Cycle 6257A–ATARM–20-Feb-08 ...
Page 109
... The VRRSTS bit is set in the Supply Controller Status Register, SUPC_SR, so that the user can know the source of the last reset. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 30 Slow Clock Cycles = about 1 ms Section 17.3.4 ”Backup Power Supply at least 1 Slow Clock Cycle Reset” ...
Page 110
... If SHDWEOF is set, the sequence is exactly the same, except the end_of_frame signal shall be asserted for at least one slow clock cycle before the lcd_nreset signal is asserted and the charge pump is disabled. The shutdown sequence led by writing SHDWEOF is described in AT91SAM7L128/64 Preliminary 110 Figure 17-6 on page 111. ...
Page 111
... Figure 17-6. Shutdown of the Backup Power Supply After Writing SHDW at 1 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary slow_clock write_shdw write_shdw_slck vddcore_nreset vr_standby flash_off flash_poe VDDCORE sram_on lcd_nreset lcd_pump_on rt_nreset rt_on supply_on VDDBU 111 ...
Page 112
... The programmer can switch off the voltage regulator, and thus put the device in Backup Mode, by writing the Supply Controller Control Register, SUPC_CR, with the VROFF bit at 1. This asserts the vddcore_nreset signal after the write resynchronization time which lasts, in the worse AT91SAM7L128/64 Preliminary 112 slow_clock ...
Page 113
... This selection is done by the LCDMODE field in the SUPC_MR register. After a backup reset, the LCDMODE field is at 0x0, it means that no power supply source is selected and the LCD Controller reset signal, lcd_nreset is asserted. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Figure 17-2 on page 107). 113 ...
Page 114
... Before setting FLASHON the user needs to program SUPC_FWUT correctly. Based on this counter the Supply Controller will correctly manage the control of the Flash Memory (refer to the wake-up time of the Flash Memory in the Electrical Characteristics section of the product datasheet). AT91SAM7L128/64 Preliminary 114 6257A–ATARM–20-Feb-08 ...
Page 115
... Wake Up Sources The wake up events allow the device to exit backup mode. When a wake up event is detected, the Supply Controller performs a sequence which automatically reenables the core power sup- ply, and the SRAM power supply not already enabled. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 115 ...
Page 116
... The wake up inputs, WKUP0 to WKUP15, can be programmed to perform a wake up of the core power supply. Each input can be enabled by writing to 1 the corresponding bit, WKUPEN0 to WKUPEN 15, in the Wake Up Inputs Register, SUPC_WUIR. The wake up level can be selected with the corresponding polarity bit, WKUPPL0 to WKUPPL15, also located in SUPC_WUIR. AT91SAM7L128/64 Preliminary 116 SLCK FWUPEN ...
Page 117
... BROWNOUT bit provides real time information, which is updated at each measurement cycle or updated at each Slow Clock cycle, if the measurement is continuous • the BODS bit provides saved information and shows a brownout has occurred since the last read of SUPC_SR 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Figure 17-8, 117 ...
Page 118
... Supply Controller Mode Register 0x0C Supply Controller Wake Up Mode Register 0x10 Supply Controller Wake Up Inputs Register 0x14 Supply Controller Status Register 0x18 Supply Controller Flash Wake-up Timer Register 0x1C Reserved AT91SAM7L128/64 Preliminary 118 Name Access SUPC_CR Write-only SUPC_BOMR Read-write SUPC_MR Read-write SUPC_WUMR ...
Page 119
... If KEY is correct, asserts vddcore_nreset and stops the voltage regulator.. • XTALSEL: Crystal Oscillator Select effect KEY is correct, switches the slow clock on the crystal oscillator output. • KEY: Password Should be written to value 0xA5. Writing any other value in this field aborts the write operation. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary KEY – ...
Page 120
... Continuous Brownout Detector 0x2 Brownout Detector enabled one SLCK period every 32 SLCK periods 0x3 Brownout Detector enabled one SLCK period every 256 SLCK periods 0x4 Brownout Detector enabled one SLCK period every 2,048 SLCK periods 0x5-0x7 Reserved AT91SAM7L128/64 Preliminary 120 – – – 21 ...
Page 121
... BODRSTEN: Brownout Reset Enable 0 = The core reset signal, vddcore_nreset is not affected when a brownout occurs The core reset signal, vddcore_nreset is asserted when a brownout occurs. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 121 ...
Page 122
... V 0xF 3.400 V • LCDMODE: LCD Power Supply Mode LCDMODE LCD Controller Power Supply The internal supply source and the external supply source are both deselected and the on-chip charge 0x0 pump is turned off. AT91SAM7L128/64 Preliminary 122 KEY – OSCBYPASS ...
Page 123
... No effect. Clock selection depends on XTALSEL value The 32-KHz XTAL oscillator is selected and is put in bypass mode. • KEY: Password Key Should be written to value 0xA5. Writing any other value in this field aborts the write operation. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Reserved Reserved 1.55V 1.65V 1 ...
Page 124
... WUPDBC: Wake Up Inputs Debouncer WUPDBC Wake Up Inputs Debouncer 0x0 Immediate, no debouncing, detected active at least on one Slow Clock edge. 0x1 An enabled wake-up input shall be active for at least 3 SLCK periods 0x2 An enabled wake-up input shall be active for at least 32 SLCK periods AT91SAM7L128/64 Preliminary 124 – – – 21 ...
Page 125
... An enabled wake-up input shall be active for at least 512 SLCK periods 0x4 An enabled wake-up input shall be active for at least 4,096 SLCK periods 0x5 An enabled wake-up input shall be active for at least 32,768 SLCK periods 0x6-0x7 Reserved 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 125 ...
Page 126
... WKUPT0 - WKUPT15: Wake Up Input Transition high to low level transition on the corresponding wake-up input forces the wake up of the core power supply low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. AT91SAM7L128/64 Preliminary 126 29 ...
Page 127
... At least one brownout has been detected since the last read of SUPC_SR. • BROWNOUT: Brownout Detector Output Status 0 = The brownout detector detected VDDIO1 higher than its threshold at its last measurement The brownout detector detected VDDIO1 lower than its threshold at its last measurement. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 29 28 WKUPIS12 WKUPIS11 ...
Page 128
... FWUP input is tied high. • WKUPIS0-WKUPIS15: WKUP Input Status The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event The corresponding wake-up input was active at the time the debouncer triggered a wake up event. AT91SAM7L128/64 Preliminary 128 6257A–ATARM–20-Feb-08 ...
Page 129
... FWUT = (Maximum wake-up time of the Flash Memory in µs) x (Maximum Master Clock Frequency during the wake-up of the Flash Memory in MHz)/ 2. This number must be rounded up. The value 0 is not allowed. For example, for a maximum wake-up time of 60 µs, and a maximum MCK frequency of 3 MHz during the wake up, FWUP is 0x5A. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – – ...
Page 130
... AT91SAM7L128/64 Preliminary 130 6257A–ATARM–20-Feb-08 ...
Page 131
... ARM7TDMI processor and the Peripheral DMA Controller. It features a bus arbiter, an address decoder, an abort status, a misalignment detector and an Embedded Flash Controller. 18.2 Block Diagram Figure 18-1. Memory Controller Block Diagram ARM7TDMI Processor Abort Peripheral DMA Controller 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Memory Controller ASB Abort Status Misalignment Bus Detector Arbiter User Interface APB ...
Page 132
... One 256-Mbyte address space reserved for the embedded peripherals • An undefined address space of 3584 Mbytes representing fourteen 256-Mbyte areas that return an Abort if accessed Figure 18-2 Figure 18-2. Memory Areas AT91SAM7L128/64 Preliminary 132 shows the assignment of the 256-Mbyte memory areas. 0x0000 0000 256 Mbytes ...
Page 133
... Kbytes contiguously at address 0x002F F000. Figure 18-3 GPNVM Bit 0 state. Figure 18-3. Internal Memory Mapping with GPNVM Bit 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary and Figure 18-4 illustrate the Internal memory mapping in accrodance to the 0x0000 0000 ROM Before Remap ...
Page 134
... The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in MC_ASR and include: • the size of the request (field ABTSZ) • the type of the access, whether data read or write code fetch (field ABTTYP) AT91SAM7L128/64 Preliminary 134 0x0000 0000 Flash Before Remap ...
Page 135
... As the requested address is saved in the Abort Status Register and the address of the instruc- tion generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 135 ...
Page 136
... Memory Controller (MC) Register Mapping Offset Register 0x00 MC Remap Control Register 0x04 MC Abort Status Register 0x08 MC Abort Address Status Register 0x10-0x5C Reserved 0x60 EFC0 Configuration Registers AT91SAM7L128/64 Preliminary 136 Name Access MC_RCR Write-only MC_ASR Read-only MC_AASR Read-only See the Embedded Flash Controller Section Reset 0x0 0x0 6257A– ...
Page 137
... RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – – – – – ...
Page 138
... ABTSZ • ABTTYP: Abort Type Status ABTTYP • MST_EMAC: EMAC Abort Source 0: The last aborted access was not due to the EMAC. 1: The last aborted access was due to the EMAC. AT91SAM7L128/64 Preliminary 138 – – – – – – – – – ...
Page 139
... At least one abort due to the PDC occurred since the last read of MC_ASR. • SVMST_ARM: Saved ARM Abort Source 0: No abort due to the ARM occurred since the last read of MC_ASR notified in the bit MST_ARM least one abort due to the ARM occurred since the last read of MC_ASR. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 139 ...
Page 140
... MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Offset: 0x08 • ABTADD: Abort Address This field contains the address of the last aborted access. AT91SAM7L128/64 Preliminary 140 ABTADD ABTADD ABTADD ABTADD 6257A–ATARM–20-Feb-08 ...
Page 141
... The embedded Flash size, the page size, the lock regions organization and GPNVM bits defini- tion are described in the product definition section. The Enhanced Embedded Flash Controller (EEFC) returns a descriptor of the Flash controlled after a get descriptor command issued by the application (see 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary “Getting Embedded Flash Descriptor” on page 147). 141 ...
Page 142
... Figure 19-1. Embedded Flash Organization Start Address + Flash size -1 AT91SAM7L128/64 Preliminary 142 Memory Plane Page 0 Start Address Page (m-1) Page (n*m-1) Lock Region 0 Lock Bit 0 Lock Region 1 Lock Bit 1 Lock Region (n-1) Lock Bit (n-1) 6257A–ATARM–20-Feb-08 ...
Page 143
... Data To ARM XXX Bytes 0-3 Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Immediate consecutive code read accesses are not mandatory to benefit from this optimization. @Byte 16 @Byte 8 @Byte 12 Bytes 16-31 Bytes 0-15 ...
Page 144
... XXX Buffer 1 (128bits) Data To ARM XXX Note: When FWS is included between 4 and 10, in case of sequential reads, the first access takes (FWS+1) cycles, each first access of the 128-bit read (FWS-2) cycles, and the others only 1 cycle. AT91SAM7L128/64 Preliminary 144 @20 @ @12 @16 Bytes 16-31 ...
Page 145
... Erase page and write page Erase page and write page then lock Erase all Set Lock Bit Clear Lock Bit Get Lock Bit 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary No consecutive data read accesses are mandatory to benefit from this optimization Bytes 0-15 4-7 ...
Page 146
... When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane, but the FLOCKE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register. AT91SAM7L128/64 Preliminary 146 Set of Commands (Continued) ...
Page 147
... MC_FRR register provide the following word of the descriptor. If extra read operations to the MC_FRR register are done after the last word of the descriptor has been returned, then the MC_FRR register value is 0 until the next valid command . 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Read Status: MC_FSR No Check if FRDY flag Set Yes ...
Page 148
... If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Two errors can be detected in the MC_FSR register after a programming sequence: • a Command Error: a bad keyword has been written in the MC_FCR register. AT91SAM7L128/64 Preliminary 148 Word Index 0 ...
Page 149
... Flash memory plane. They prevent writing/erasing protected pages. The lock sequence is: • The Set Lock command (SLB) and a page number to be protected are written in the Flash Command Register. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Figure 19-7). 32-bit wide FF FF ...
Page 150
... Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with the SGPB command and the number of the GPNVM bit to be set. AT91SAM7L128/64 Preliminary 150 Access to the Flash in read is permitted when a set, clear or get lock bit command is performed. ...
Page 151
... Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Access to the Flash in read is permitted when a set, clear or get GPNVM bit command is performed. 151 ...
Page 152
... Table 19-3. Register Mapping Offset Register MC 0x00 Flash Mode Register MC 0x04 Flash Command Register MC 0x08 Flash Status Register MC 0x0C Flash Result Register 0x10 Reserved AT91SAM7L128/64 Preliminary 152 Name Access MC _FMR Read-write MC _FCR Write-only MC _FSR Read-only MC _FRR Read-only – – Reset State 0x0 – ...
Page 153
... Flash Ready does not generate an interrupt. 1: Flash Ready (to accept a new command) generates an interrupt. • FWS: Flash Wait State This field defines the number of wait states for read and write operations: Number of cycles for Read/Write operations = FWS+1 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – – ...
Page 154
... Field is meaningless. • FKEY: Flash Writing Protection Key This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is writ- ten with a different value, the write is not performed and no action is started. AT91SAM7L128/64 Preliminary 154 29 28 ...
Page 155
... No programming/erase of at least one locked region has happened since the last read of MC_FSR. 1: Programming/erase of at least one locked region has happened since the last read of MC_FSR. This flag is automatically cleared when MC_FSR is read or MC_FCR is written. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – ...
Page 156
... Access Type: Read-only Offset: 0x6C • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read. AT91SAM7L128/64 Preliminary 156 FVALUE FVALUE FVALUE 5 ...
Page 157
... Parallel Fast Flash Programming 20.2.1 Device Configuration In Fast Flash Programming Mode, the device specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected. Figure 20-1. Parallel Programming Interface 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary VDDIO1 TST VDDIO1 CLKIN GND FWUP ...
Page 158
... PGMNOE Output Enable (active high) 0: DATA[15: input mode PGMNVALID 1: DATA[15: output mode PGMM[3:0] Specifies DATA type (See PGMD[15:0] Bi-directional data bus Note: 1. See Figure 20-2 below. AT91SAM7L128/64 Preliminary 158 Active Type Level Power Power Power Power Power Power Power Power Ground ...
Page 159
... When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. Table 20-3. DATA[15:0] 0x0011 0x0012 0x0022 0x0032 0x0042 0x0013 0x0014 0x0024 0x0015 0x0034 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary External supply VDDIO2 VDDLCD VDD3V6 VDDINLCD Mode Coding Symbol CMDE ADDR0 ADDR1 DATA IDLE Command Bit Coding Symbol ...
Page 160
... NCMD signal. The handshaking is achieved once NCMD signal is high and RDY is high. 20.2.4.1 Write Handshaking For details on the write handshaking sequence, refer to Figure 20-3. Parallel Programming Timing, Write Sequence AT91SAM7L128/64 Preliminary 160 Command Bit Coding (Continued) Symbol CGPB GGPB ...
Page 161
... Clears NOE signal 6 Waits for NVALID low 7 8 Reads value on DATA Bus 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Device Action Waits for NCMD low Latches MODE and DATA Clears RDY signal Executes command and polls NCMD high Executes command and polls NCMD high ...
Page 162
... Flash memory page. The load buffer is automatically flushed to the Flash: • before access to any page other than the current one • when a new command is validated (MODE = CMDE) AT91SAM7L128/64 Preliminary 162 Device Action Sets DATA bus in input mode ...
Page 163
... Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is pro- vided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is activated. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Write Command Handshake Sequence MODE[3:0] ...
Page 164
... A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. AT91SAM7L128/64 Preliminary 164 Set and Clear Lock Bit Command ...
Page 165
... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-15. Get Version Command Step 1 2 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Handshake Sequence Write handshaking Write handshaking Handshake Sequence MODE[3:0] Write handshaking CMDE Write handshaking ...
Page 166
... Charge pump output VDDLCD LCD voltage input GND Ground XIN Clock Input TST Test Mode Select External clock input used to enter in CLKIN FFPI mode FWUP Wake-up pin AT91SAM7L128/64 Preliminary 166 VDDIO1 TST VDDIO1 CLKIN GND FWUP TDI TDO TMS TCK 0-10MHz XIN ...
Page 167
... Shift 0x2 into the DR register ( bits long, LSB first) without going through the Run- Test-Idle state. • Shift 0xC into the IR register ( bits long, LSB first) without going through the Run-Test- Idle state. Note: 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Type JTAG Input Input Output ...
Page 168
... The address of the Debug Comms Data Register is 0x05. The Debug Comms Control Register is read-only and allows synchronized handshaking between the processor and the debugger. – Bit 1 (W): Denotes whether the programmer can read a data through the Debug AT91SAM7L128/64 Preliminary 168 TDI TMS ...
Page 169
... Write Write Write 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Data Register data previously placed there through the scan chain has not been collected by the device and so the programmer must wait. 159. Commands are run by the programmer through the serial interface that DR Data (Number of Words to Read) < ...
Page 170
... Lock bits can be read using Get Lock Bit command (GLB). When a bit set in the Bit Mask is returned, then the corresponding lock bit is active. Table 20-22. Get Lock Bit Command Read/Write Write Read AT91SAM7L128/64 Preliminary 170 DR Data Memory [address+4] Memory [address+8] Memory [address+(Number of Words to Write - 1)* 4] ...
Page 171
... Memory Write Command This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. An internal address buffer is automatically increased. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary DR Data SGPB or CGPB Bit Mask DR Data GGPB Bit Mask ...
Page 172
... Write 20.3.4.8 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-27. Get Version Command Read/Write Write Read AT91SAM7L128/64 Preliminary 172 DR Data (Number of Words to Write) << (WRAM) Address Memory [address] Memory [address+4] Memory [address+8] Memory [address+(Number of Words to Write - 1)* 4] ...
Page 173
... C variable initialization 7. Disable of the Watchdog and enable of the user reset 8. Jump to SAM-BA Boot sequence (see 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary ® Boot is executed at power-up only, if the device exits OFF mode and if the GPNVM bit ™ Boot first initializes the Debug Unit serial port (DBGU) and the PLL fre- ...
Page 174
... SAM-BA Boot The SAM-BA boot principle is to: – Check if the AutoBaudrate sequence has succeeded (see – Check if characters have been received on the DBGU Figure 21-2. AutoBaudrate Flow Diagram AT91SAM7L128/64 Preliminary 174 Device Setup No Character '0x80' received ? Yes Define baudrate divisor value ...
Page 175
... The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary loop waiting for different commands as given in Commands Available through the SAM-BA Boot ...
Page 176
... CRC16 Figure 21-3 Figure 21-3. Xmodem Transfer Example 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary to 01) shows a transmission using this protocol. Host SOH 01 FE Data[128] CRC CRC SOH 02 FD Data[128] CRC CRC ...
Page 177
... Send your data to the sector */ /* build the command to send to EFC */ /* Call the IAP function with appropriate command */ } 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary unsigned long FlashSectorNum = 200; unsigned long flash_cmd = 0; unsigned long flash_status = 0; IAP_Function = ((unsigned long) (*)(unsigned long)) 0x400008; flash_cmd = (0x5A << 24) | (FlashSectorNum << AT91C_MC_FCMD_EWP; ...
Page 178
... DBGU Using a 32.768 KHz crystal is not mandatory since SAM-BA boot will automatically use the inter- nal 32Khz RC oscillator. PLL MUL parameter is automatically adapted to provide 115200 baudrate on the DBGU serial port. AT91SAM7L128/64 Preliminary 178 Pins Driven during Boot Program Execution Pin DRXD ...
Page 179
... The peripheral triggers PDC transfers using transmit and receive signals. When the pro- grammed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral. 22.2 Block Diagram Figure 22-1. Block Diagram 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Peripheral DMA Controller Peripheral THR PDC Channel 0 PDC Channel 1 RHR Status & ...
Page 180
... These counters are decremented after each data transfer. When the counter reaches zero, the transfer is complete and the PDC stops transfer- ring data. If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag. AT91SAM7L128/64 Preliminary 180 6257A–ATARM–20-Feb-08 ...
Page 181
... If simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 181 ...
Page 182
... PDC Transfer Status Register Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc). AT91SAM7L128/64 Preliminary 182 Register Name Access ...
Page 183
... RXPTR: Receive Pointer Address Address of the next receive transfer. 22.4.2 PDC Receive Counter Register Register Name: PERIPH_RCR Access Type: Read-write • RXCTR: Receive Counter Value Number of receive transfers to be performed. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary RXPTR RXPTR RXPTR RXPTR 29 28 ...
Page 184
... Address of the transmit buffer. 22.4.4 PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: Read-write • TXCTR: Transmit Counter Value TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral data transfer is stopped. AT91SAM7L128/64 Preliminary 184 TXPTR TXPTR TXPTR TXPTR ...
Page 185
... RXNPTR is the address of the next buffer to fill with received data when the current buffer is full. 22.4.6 PDC Receive Next Counter Register Register Name: PERIPH_RNCR Access Type: Read-write • RXNCR: Receive Next Counter Value RXNCR is the size of the next buffer to receive. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary RXNPTR RXNPTR RXNPTR RXNPTR 29 ...
Page 186
... TXNPTR is the address of the next buffer to transmit when the current buffer is empty. 22.4.8 PDC Transmit Next Counter Register Register Name: PERIPH_TNCR Access Type: Read-write • TXNCR: Transmit Next Counter Value TXNCR is the size of the next buffer to transmit. AT91SAM7L128/64 Preliminary 186 TXNPTR TXNPTR TXNPTR ...
Page 187
... RXTDIS: Receiver Transfer Disable effect Disables the receiver PDC transfer requests. • TXTEN: Transmitter Transfer Enable effect Enables the transmitter PDC transfer requests. • TXTDIS: Transmitter Transfer Disable effect Disables the transmitter PDC transfer requests 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary – – – – ...
Page 188
... RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled Receiver PDC transfer requests are enabled. • TXTEN: Transmitter Transfer Enable 0 = Transmitter PDC transfer requests are disabled Transmitter PDC transfer requests are enabled. AT91SAM7L128/64 Preliminary 188 – – – ...
Page 189
... Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. The fast forcing feature redirects any internal or external interrupt source to provide a fast inter- rupt rather than a normal interrupt. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary 189 ...
Page 190
... Block Diagram Figure 23-1. Block Diagram 23.3 Application Block Diagram Figure 23-2. Description of the Application Block 23.4 AIC Detailed Block Diagram Figure 23-3. AIC Detailed Block Diagram AT91SAM7L128/64 Preliminary 190 FIQ IRQ0-IRQn Embedded PeripheralEE Embedded Peripheral Embedded Peripheral Standalone OS Drivers ...
Page 191
... Consequently, to sim- plify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Pin Description Fast Interrupt Interrupt 0 - Interrupt n ...
Page 192
... The AIC_ISR register reads the number of the current interrupt (see 195) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. AT91SAM7L128/64 Preliminary 192 (See “Priority Controller” on page 195.) The automatic clear reduces See “ ...
Page 193
... Internal Interrupt Source Input Stage Figure 23-4. 23.7.1.6 External Interrupt Source Input Stage Figure 23-5. External Interrupt Source Input Stage Source i AIC_ISCR AIC_ICCR 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Source i Edge Edge Detector Set ...
Page 194
... The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 23.7.2.1 External Interrupt Edge Triggered Source Figure 23-6. 23.7.2.2 External Interrupt Level Sensitive Source Figure 23-7. AT91SAM7L128/64 Preliminary 194 External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) ...
Page 195
... The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4 ...
Page 196
... This section gives an overview of the fast interrupt handling sequence when using the AIC assumed that the programmer understands the architecture of the ARM processor, and espe- cially the processor interrupt modes and the associated status bits. AT91SAM7L128/64 Preliminary 196 PC,[PC,# -&F20] 6257A–ATARM–20-Feb-08 ...
Page 197
... CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary priority. The current level is the priority level of the current interrupt. must be read in order to de-assert nIRQ. If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared dur- ing this phase ...
Page 198
... The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In AT91SAM7L128/64 Preliminary 198 The “I” bit in SPSR is significant set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted ...
Page 199
... The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Reg- ister (AIC_IPR). 6257A–ATARM–20-Feb-08 AT91SAM7L128/64 Preliminary The “F” bit in SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked) ...
Page 200
... AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. AT91SAM7L128/64 Preliminary 200 _ FIQ ...