AT91SAM7L128-CU Atmel, AT91SAM7L128-CU Datasheet - Page 270

• Manufacturer Part Number: AT91SAM7L128-CU
• Description: MCU ARM7 128K HS FLASH 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7L128-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 36MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.55 V ~ 1.8 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 6 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

27.4
Figure 27-3. I/O Line Control Logic
270
Output Enable
Output Enable
Peripheral A
Peripheral B
Functional Description
Peripheral A
Peripheral B
PIO_BSR[0]
PIO_ASR[0]
AT91SAM7L128/64 Preliminary
Output
Output
PIO_ABSR[0]
PIO_OER[0]
PIO_ODR[0]
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic asso-
ciated to each I/O is represented in
represents but one of up to 32 possible indexes.
1
1
0
0
PIO_OSR[0]
PIO_IFER[0]
PIO_IFDR[0]
PIO_SODR[0]
PIO_CODR[0]
PIO_IFSR[0]
PIO_PER[0]
PIO_PDR[0]
Glitch
Filter
PIO_ODSR[0]
PIO_PSR[0]
PIO_PDSR[0]
1
0
PIO_IER[31]
PIO_IDR[31]
PIO_IER[0]
PIO_IDR[0]
1
0
1
0
Detector
Edge
PIO_IMR[31]
PIO_ISR[31]
PIO_IMR[0]
PIO_ISR[0]
PIO_MDER[0]
PIO_MDDR[0]
Figure
PIO_MDSR[0]
27-3. In this description each signal shown
(Up to 32 possible inputs)
1
0
0
1
PIO_PUER[0]
PIO_PUDR[0]
PIO_PUSR[0]
PIO Interrupt
Peripheral B
Peripheral A
Input
Input
6257A–ATARM–20-Feb-08
Pad