LH79520N0Q000B1;55 NXP Semiconductors, LH79520N0Q000B1;55 Datasheet - Page 16

• Manufacturer Part Number: LH79520N0Q000B1;55
• Description: IC ARM7 BLUESTREAK MCU 176LQFP
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH79520N0Q000B1;55

• Package / Case: 176-LQFP
• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 77.4MHz
• Connectivity: EBI/EMI, IrDA, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH795
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, UART
• Maximum Clock Frequency: 77.4 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4331; 935285044557; LH79520N0Q000B1

LH79520
SYSTEM DESCRIPTIONS
ARM720T Processor
cached core with an Advanced High-Performance Bus
(AHB) interface. The ARM720T features:
• 32-bit ARM7TDMI™ RISC Core
• 8 kB Cache
• MMU (Windows CE enabled)
processors. For more information, see the ARM docu-
ment, ‘ARM720T (Rev 3) Technical Reference Manual’,
available on NXP’s’s website at www.nxp.com.
ical Memory (PA) addresses to virtual memory
addresses. This allows physical memory, which is con-
16
The LH79520 microcontroller features the ARM720T
The processor is a member of the ARM7T family of
The LH79520 MMU provides a means to map Phys-
IMAGER
INTERFACE
MEMORY
Figure 3. LH79520 Application Diagram Example
CARD
FLASH/
SRAM/
SDRAM
DMA
Rev. 01 — 16 July 2007
NXP Semiconductors
CODEC
SSP
UART
strained by hardware to specific addresses, to be reor-
ganized at addresses identified by the user. These user
identified locations are called Virtual Addresses (VA).
When the MMU is enabled, Code and Data must be
built, loaded, and executed using Virtual Addresses
which the MMU translates to Physical Addresses. In
addition, the user may implement a memory protection
scheme by using the features of the MMU. Address
translation and memory protection services provided
by the MMU are controlled by the user. The MMU is
directly controlled through the System Control Copro-
cessor, Coprocessor 15 (CP15). The MMU is indirectly
controlled by a Translation Table (TT) and Page Tables
(PT) prepared by the user and established using a por-
tion of physical memory dedicated by the user to stor-
ing the TT and PT’s.
STN/
TFT/AD-TFT
LH79520
PWM
IR
PIO
SCREEN
CONTR.
TOUCH
UART
Preliminary data sheet
System-on-Chip
79520-6A