LH79520N0Q000B1;55 NXP Semiconductors, LH79520N0Q000B1;55 Datasheet - Page 37

• Manufacturer Part Number: LH79520N0Q000B1;55
• Description: IC ARM7 BLUESTREAK MCU 176LQFP
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH79520N0Q000B1;55

• Package / Case: 176-LQFP
• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 77.4MHz
• Connectivity: EBI/EMI, IrDA, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH795
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, UART
• Maximum Clock Frequency: 77.4 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4331; 935285044557; LH79520N0Q000B1

System-on-Chip
SDRAM Memory Controller Waveforms
SDRAM Burst Read (page already open). Figure 17
shows the waveform and timing for SDRAM to Activate
a Bank and Write.
Preliminary data sheet
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is LOW.
5. SDCKE is HIGH.
SDRAMcmd
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is LOW.
Figure 16 shows the waveform and timing for an
SDRAMcmd
A[15:0]
D[31:0]
SCLK
SDCKE
D[31:0]
A[15:0]
SCLK
t SDCLK
tSDCLK
Figure 17. SDRAM Bank Activate and Write
t OVXXX
tOVA
READ
Figure 16. SDRAM Burst Read
COLUMN
BANK,
t OHXXX
t OV
tOVC0
Rev. 01 — 16 July 2007
NXP Semiconductors
tOVA
tOVXXX
ACTIVE
tISD tIHD
tOVA
BANK,
tOHXXX
ROW
DATA n
DATA n + 1
DATA n + 2
DATA n + 3
tOVD
WRITE
COLUMN
DATA
BANK,
tOHD
LH79520
LH79520-35
79520-36
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