LH79520N0Q000B1;55 NXP Semiconductors, LH79520N0Q000B1;55 Datasheet - Page 38

• Manufacturer Part Number: LH79520N0Q000B1;55
• Description: IC ARM7 BLUESTREAK MCU 176LQFP
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH79520N0Q000B1;55

• Package / Case: 176-LQFP
• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 77.4MHz
• Connectivity: EBI/EMI, IrDA, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH795
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, UART
• Maximum Clock Frequency: 77.4 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4331; 935285044557; LH79520N0Q000B1

LH79520
External DMA Handshake Signal Timing
DREQ TIMING
DREQ1 must not transition from LOW to HIGH again
until after nDACK0 or DACK1 has been asserted.
DACK/DEOT TIMING
DACK1, DEOT0 and DEOT1 occur in relation to an
external bus access to/from the external peripheral that
requested the DMA transfer.
38
NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN.
As Figure 18 shows, once asserted, DREQ0 or
These timing diagrams indicate when nDACK0,
tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
n DACK0
DREQ0,
DREQ1
DACK1
Figure 18. DREQ Timing Restrictions
CHANGE STATE
Rev. 01 — 16 July 2007
MUST NOT
NXP Semiconductors
DREQ
TRANSITON
DREQ MAY
read or the last word of a burst read from the requesting
peripheral. Figure 20 shows the timing with relation to
a single write or the last word of a burst write to the
requesting peripheral.
able when a Write to SDRAM occurs just prior to a sin-
gle word Write to the requesting peripheral. If the write
buffer is enabled for the SDRAM Controller, this can
cause the DACK/DEOT to occur an indeterminate
number of cycles prior to the actual Write to the
requesting peripheral.
Figure 19 shows the timing with relation to a single
The timing of DACK/DEOT may become unpredict-
tDREQ0L,
tDREQ1L
Preliminary data sheet
System-on-Chip
79520-158