LH79520N0Q000B1;55 NXP Semiconductors, LH79520N0Q000B1;55 Datasheet - Page 47

• Manufacturer Part Number: LH79520N0Q000B1;55
• Description: IC ARM7 BLUESTREAK MCU 176LQFP
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH79520N0Q000B1;55

• Package / Case: 176-LQFP
• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 77.4MHz
• Connectivity: EBI/EMI, IrDA, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LH795
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: JTAG, UART
• Maximum Clock Frequency: 77.4 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4331; 935285044557; LH79520N0Q000B1

System-on-Chip
Preliminary data sheet
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
NOTE:
133
137
131
(Gate Driver Clock)
LCDVD[17:0]
(LCD DATA)
LCDVD[17:0]
(DELAYED FOR HR-TFT)
LCDLP
(HORIZONTAL SYNC PULSE)
CLCDC CLOCK
(INTERNAL)
PERIPHCLKSEL2:LCSRC
PERIPHCLKCTRL2:LCDCLK
LCDCLKPRESCALE:LCDPSVAL
(SHOWN FOR REFERENCE)
(Vertical Sync)
LCDENAB
(INTERNAL DATA ENABLE)
LCDDCLK
(DELAYED FOR HR-TFT)
LCDSPL
(LINE START PULSE LEFT)
LCDLP
(HORIZONTAL SYNC PULSE)
LCDSPS
LCDCLS
Circled numbers are LH79520 pin numbers.
LCDDCLK
(PANEL DATA CLOCK)
TIMING2:PCD
TIMING2:BCD
TIMING2:IPC
TIMING2:CPL
LCDMux:PIN133
LCDVD[17:0]
16 × (TIMING0:PPL+1)
142
119
135
Figure 27. AD-TFT and HR-TFT Horizontal Timing Diagram
LCDREV
LCDPS
LCDCLS
Figure 28. AD-TFT and HR-TFT Vertical Timing Diagram
1.5 µs - 4 µs
TIMING1:VSW
TIMING0:HSW
ALITIMING1:PSCLS
ALITIMING1:LPDEL
TIMING0:HSW +
ALITIMING2:SPLDEL
TIMING0:HBP
Rev. 01 — 16 July 2007
NXP Semiconductors
1 LCDDCLK
1 LCDDCLK
001
002 003 004 005 006 007 008
001
1 AD-TFT or HR-TFT HORIZONTAL LINE
ALITIMING2:PS2CLS2
002 003 004 005 006
PIXEL DATA
ALITIMING1:REVDEL
320
317
318
319 320
79520-120
79520-20
LH79520
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