LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 239

• Manufacturer Part Number: LPC2478FBD208,551
• Description: IC ARM7 MCU 512K LCD 208-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2478FBD208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-LQFP
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
• Development Tools By Supplier: OM11015, OM11019, OM11022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4363; 935284069551; LPC2478FBD208-S

NXP Semiconductors
UM10237_4
User manual
7.4.2 Interrupt Enable Register (IntEnable - 0xFFE0 0FE4)
Table 228. Interrupt Status register (IntStatus - address 0xFFE0 0FE0) bit description
The interrupt status register is read-only. Setting can be done via the IntSet register. Reset
can be accomplished via the IntClear register.
The Interrupt Enable register (IntEnable) has an address of 0xFFE0 0FE4. The interrupt
enable register bit definition is shown in
Table 229. Interrupt Enable register (intEnable - address 0xFFE0 0FE4) bit description
Bit
0
1
2
3
4
5
6
7
11:8
12
13
31:14
Bit
0
1
2
3
Symbol
RxOverrunInt
RxErrorInt
RxFinishedInt
RxDoneInt
TxUnderrunInt Interrupt set on a fatal underrun error in the transmit queue. The
TxErrorInt
TxFinishedInt
TxDoneInt
-
SoftInt
WakeupInt
-
Symbol
RxOverrunIntEn
RxErrorIntEn
RxFinishedIntEn
RxDoneIntEn
Rev. 04 — 26 August 2009
Function
Interrupt set on a fatal overrun error in the receive queue. The
fatal interrupt should be resolved by a Rx soft-reset. The bit is not
set when there is a nonfatal overrun error.
Interrupt trigger on receive errors: AlignmentError, RangeError,
LengthError, SymbolError, CRCError or NoDescriptor or Overrun.
Interrupt triggered when all receive descriptors have been
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
Interrupt triggered when a receive descriptor has been processed
while the Interrupt bit in the Control field of the descriptor was set.
fatal interrupt should be resolved by a Tx soft-reset. The bit is not
set when there is a nonfatal underrun error.
Interrupt trigger on transmit errors: LateCollision,
ExcessiveCollision and ExcessiveDefer, NoDescriptor or
Underrun.
Interrupt triggered when all transmit descriptors have been
processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
Interrupt triggered when a descriptor has been transmitted while
the Interrupt bit in the Control field of the descriptor was set.
Unused
Interrupt triggered by software writing a 1 to the SoftintSet bit in
the IntSet register.
Interrupt triggered by a Wakeup event detected by the receive
filter.
Unused
Function
Enable for interrupt trigger on receive buffer overrun or
Enable for interrupt triggered when all receive descriptors have
Enable for interrupt triggered when a receive descriptor has
descriptor underrun situations.
Enable for interrupt trigger on receive errors.
been processed i.e. on the transition to the situation where
ProduceIndex == ConsumeIndex.
been processed while the Interrupt bit in the Control field of the
descriptor was set.
Table
11–229.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
239 of 792
Reset
value
0
0
0
0
0
0
0
0
0x0
0
0
0x0
Reset
value
0
0
0
0