MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet
MC908LD64IFUE
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MC908LD64IFUE Summary of contents
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MC68HC908LD64 Data Sheet M68HC08 Microcontrollers MC68HC908LD64 Rev. 3.0 07/2004 freescale.com ...
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...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. MC68HC908LD64 Rev. 3.0 — ...
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... Revision History Description — Removed incorrect — Corrected HALFCLK — Corrected WRDY bit — Corrected — Corrected OSD_EN bit — Corrected timer — Changed the prefix "D" to Page Number(s) 179 278 278 279 288 149 235 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... Section 21. Keyboard Interrupt Module (KBI 321 Section 22. Computer Operating Properly (COP 329 Section 23. Break Module (BRK 335 Section 24. Electrical Specifications 343 Section 25. Mechanical Specifications . . . . . . . . . . . . . 357 Section 26. Ordering Information . . . . . . . . . . . . . . . . . 359 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor List of Sections List of Sections Data Sheet 5 ...
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... List of Sections Data Sheet 6 MC68HC908LD64 List of Sections Rev. 3.0 — Freescale Semiconductor ...
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... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Section 2. Memory Map Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 41 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Input/Output (I/O) Section Section 3 ...
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... Section 6. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table of Contents MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Section 7. Oscillator (OSC) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .96 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Crystal Amplifier Input Pin (OSC1 Crystal Amplifier Output Pin (OSC2 Oscillator Enable Signal (SIMOSCEN External Clock Source (OSCXCLK) ...
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... Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .122 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . 122 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . 122 SIM Counter and Reset States 123 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table of Contents MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor SWI Instruction 127 Interrupt Status Registers 127 Interrupt Status Register 129 Interrupt Status Register 129 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 130 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Wait Mode ...
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... TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 160 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Section 12. Pulse Width Modulator (PWM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 PWM Registers 173 PWM Data Registers (0PWM–7PWM 173 PWM Control Register (PWMCR 174 Table of Contents MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Section 13. Analog-to-Digital Converter (ADC) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Interrupts ...
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... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Multi-Master IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Multi-Master IIC Address Register (MMADR 224 Multi-Master IIC Control Register (MMCR 225 Multi-Master IIC Master Control Register (MIMCR 226 Multi-Master IIC Status Register (MMSR 228 Table of Contents MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Multi-Master IIC Data Transmit Register (MMDTR 230 Multi-Master IIC Data Receive Register (MMDRR 231 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 232 Section 16. DDC12AB Interface Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 DDC Protocols ...
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... OSD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 OSD Display Registers (Attribute and Code Registers 282 Row Attribute Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Control, Window, and Pattern Registers . . . . . . . . . . . . . . 283 Window Registers 284 Vertical Delay Control Register . . . . . . . . . . . . . . . . . . . 285 Horizontal Delay Control Register . . . . . . . . . . . . . . . . . 286 Table of Contents MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Character Height Control Register . . . . . . . . . . . . . . . . . 286 Frame Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 288 Section 19. Input/Output (I/O) Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Port 297 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Data Direction Register 298 Port A Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Port B ...
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... Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . 328 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 Power-On Reset 331 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Reset Vector Fetch 332 Table of Contents MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor COPD (COP Disable 332 COPRS (COP Rate Select 332 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Interrupts .333 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 334 Section 23 ...
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... Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 347 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Section 25. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 64-Pin Plastic Quad Flat Pack (QFP 358 Section 26. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 Table of Contents MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Title MC68HC908LD64 MCU Block Diagram 64-Pin QFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .45 FLASH I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 64 47,616-byte FLASH Control Register (FLCR 13K-byte FLASH Control Register (FLCR1 OSD FLASH Even High Byte Write Buffer (OSDEHBUF) ...
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... SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SIM I/O Register Summary .116 OSC Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 List of Figures Page MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... USB Embedded Device Control Register 2 (DCR2 216 14-19 USB Embedded Device Status Register (DSR 217 14-20 USB Embedded Device Endpoint 0 Data Registers MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Title (HDP1CR–HDP4CR 195 (DE0D0–DE0D7 219 List of Figures List of Figures Page ...
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... Hsync Frequency Low Register . . . . . . . . . . . . . . . . . . . . . . .265 17-10 Sync Processor Control Register 1 (SPCR1 267 17-11 H&V Sync Output Control Register (HVOCR 268 Data Sheet 24 Title (DE1D0–DE1D7 219 Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 249 List of Figures Page MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... Port D Control Register (PDCR 309 19-17 Port E Data Register (PTE 311 19-18 Data Direction Register E (DDRE 312 19-19 Port E I/O Circuit 312 19-20 Port E Control Register (PECR 313 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Title List of Figures List of Figures Page Data Sheet 25 ...
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... Break Address Register Low (BRKL 340 23-6 SIM Break Status Register (SBSR 341 23-7 SIM Break Flag Control Register (SBFCR 342 24-1 MMIIC Signal Timings 354 25-1 64-Pin QFP (Case #840B 358 Data Sheet 26 Title MC68HC908LD64 List of Figures Page Rev. 3.0 — Freescale Semiconductor ...
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... Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 147 11-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11-2 Prescaler Selection 163 11-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 167 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Title Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 FLASH Memory Array Summary . . . . . . . . . . . . . . . . . . . . . . . 65 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Free-Running HSOUT, VSOUT, DE, and DCLK Settings ...
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... Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 19-4 Port C Pin Functions 305 19-5 Port D Pin Functions 308 19-6 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 21-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 24-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Data Sheet 28 Title MC68HC908LD64 List of Tables Page Rev. 3.0 — Freescale Semiconductor ...
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... USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 24-15 DDC12AB/MMIIC Interface Input Signal Timing 354 24-16 DDC12AB/MMIIC Interface Output Signal Timing . . . . . . . . . 354 24-17 FLASH Memory Electrical Characteristics . . . . . . . . . . . . . . . 355 26-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Title List of Tables List of Tables Page Data Sheet 29 ...
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... List of Tables Data Sheet 30 MC68HC908LD64 List of Tables Rev. 3.0 — Freescale Semiconductor ...
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... DDC12AB interface, multi-master IIC interface, and universal serial bus interface, the MC68HC908LD64 is designed specifically for use in digital monitor systems. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 ...
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... On screen display (OSD) and full screen pattern display 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 32 sync or composite sync inputs General Description 1 feature MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... DDC is a VESA bus standard. 2. IIC is a proprietary Philips interface bus. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Full Universal Serial Bus (USB) specification 1.1, composite hub with embedded functions, including: – One 12MHz upstream port – Four 12MHz/1.5MHz downstream ports – One hub control endpoint with 8-byte transmit buffer and 8-byte receive buffer – ...
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... Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Third party C language support 1.4 MCU Block Diagram Figure 1-1 Data Sheet 34 shows the structure of the MC68HC908LD64. General Description MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... VDD2 POWER VSS2 VDDA VSSA VRH ADC REFERENCE VRL Figure 1-1. MC68HC908LD64 MCU Block Diagram MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor INTERNAL BUS KEYBOARD INTERRUPT MODULE PULSE WIDTH MODULATOR MODULE MONITOR MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE FREE-RUN PANEL TIMING MODULE SYNC PROCESSOR ...
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... PTE0/DPLUS1 8 PTE1/DMINUS1 9 PTE2/DPLUS2 10 PTE3/DMINUS2 11 PTE4/DPLUS3 12 PTE5/DMINUS3 13 PTE6/DPLUS4 14 PTE7/DMINUS4 15 CGMXFC 16 Figure 1-2. 64-Pin QFP Pin Assignment Data Sheet 36 General Description PTA3/KBI3 48 PTA2/KBI2 47 PTA1/KBI1 46 PTA0/KBI0 45 VDD2 44 PTB7/PWM7 43 PTB6/PWM6 42 PTB5/PWM5 41 PTB4/PWM4 40 PTB3/PWM3 39 PTB2/PWM2 38 PTB1/PWM1 37 PTB0/PWM0 36 PTD7IICSDA 35 PTD6/IICSCL 34 PTD5/DDCSDA 33 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... Pin Functions Description of the pin functions are provided in MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Table 1-1. Pin Functions PIN NAME VDD1, VDD2 Power supply input to the MCU. VSS1, VSS2 Power supply ground. VDDA Power supply input for analog circuits. VSSA Power supply ground for analog circuits ...
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... I/O pin or the clock line of the DDC12AB module. This pin is +5V open-drain PTD4/DDCSCL when configured as output. See Section 19. Input/Output (I/O) Ports Section 16. DDC12AB General Description PIN DESCRIPTION and (PWM). Ports. and (ADC). and (MMIIC). and (MMIIC). and Interface. and Interface. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... Any unused inputs and I/O ports should be tied to an appropriate logic level (either V require termination, termination is recommended to reduce the possibility of static damage. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Table 1-1. Pin Functions (Continued) PIN NAME These are shared function, bidirectional I/O port PTD3/HOUT pins. These pins can be configured as standard PTD2/VOUT I/O pins or free-run timing output signals ...
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... General Description Data Sheet 40 General Description MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
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... Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. In the memory map (Figure locations are shaded. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 41 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Input/Output (I/O) Section Figure 2-1, includes: ...
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... Break status and control register, BRKSCR • $FE0F; Reserved • $FFFF; COP control register, COPCTL Data registers are shown in locations. Data Sheet 42 Figure 2-1 and in register figures in this document, Figure 2-2. Table 2-1 MC68HC908LD64 Memory Map is a list of vector Rev. 3.0 — Freescale Semiconductor ...
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... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor $0000 I/O Registers ↓ 128 Bytes $007F $0080 ↓ 1,024 Bytes $047F $0480 Unimplemented ↓ 896 Bytes $07FF $0800 OSD RAM ↓ 1,024 Bytes $0BFF $0C00 FLASH Memory ↓ 1,024 Bytes (8 × 128-Byte Blocks) $0FFF ...
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... Break Address Register Low (BRKL) $FE0E Break Status and Control Register (BRKSCR) $FE0F Reserved $FE10 Monitor ROM ↓ 464 Bytes $FFDF $FFE0 FLASH Vectors ↓ 32 Bytes $FFFF Figure 2-1. Memory Map (Continued) Memory Map MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 45
... Write: (PTE) Reset: Read: Data Direction Register E $0009 Write: (DDRE) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 15) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 Unaffected by reset 0 ...
Page 46
... PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX Reserved MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 47
... Write: (DDC2ADR) Reset: Read: $001D Unimplemented Write: Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 15) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit Bit15 Bit14 Bit13 Bit12 Indeterminate after reset Bit7 Bit6 Bit5 Indeterminate after reset ALIF NAKIF ...
Page 48
... DE0T31 DE0T30 DE0R43 DE0R42 DE0R41 DE0R40 DE0T43 DE0T42 DE0T41 DE0T40 DE0R53 DE0R52 DE0R51 DE0R50 DE0T53 DE0T52 DE0T51 DE0T50 DE0R63 DE0R62 DE0R61 DE0R60 DE0T63 DE0T62 DE0T61 DE0T60 DE0R73 DE0R72 DE0R71 DE0R70 DE0T73 DE0T72 DE0T71 DE0T70 R = Reserved MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 49
... Read: HE0R17 USB HUB Endpoint 0 $0031 Data Register 1 Write: HE0T17 (HE0D1) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 15) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit DE1T06 DE1T05 DE1T04 Indeterminate after reset DE1T16 DE1T15 DE1T14 Indeterminate after reset ...
Page 50
... HE0T41 HE0T40 HE0R53 HE0R52 HE0R51 HE0R50 HE0T53 HE0T52 HE0T51 HE0T50 HE0R63 HE0R62 HE0R61 HE0R60 HE0T63 HE0T62 HE0T61 HE0T60 HE0R73 HE0R72 HE0R71 HE0R70 HE0T73 HE0T72 HE0T71 HE0T70 VRS7 VRS6 VRS5 VRS4 ADCH3 ADCH2 ADCH1 ADCH0 Reserved MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 51
... Reset: Read: VSYNCS HSYNCS Sync Processor I/O Control $0045 Register Write: (SPIOCR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 15) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit AD7 AD6 AD5 Indeterminate after reset ADIV2 ADIV1 ADIV0 DCLKPH1 DCLKPH0 ...
Page 52
... ENABLE2 ENABLE1 DSTALL2 DSTALL1 DADD3 DADD2 DADD1 DADD0 TXD0IE RXD0IE TXD0FR RXD0FR TXD1IE TXD1FR TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 Reserved MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 53
... RSTF and USBEN are reset by a power-on reset (POR) only. Read: USB HUB Interrupt $0059 Register 0 Write: (HIR0) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 15) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit PEN1 LOWSP1 RST1 RESUM1 PEN2 LOWSP2 ...
Page 54
... OSDD12 OSDD11 Unaffected by reset = Unimplemented Memory Map Bit 0 TPSIZ3 TPSIZ2 TPSIZ1 TPSIZ0 PCHG3 PCHG2 PCHG1 PCHG0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0 D0+ D0– CLKPH1 CLKPH0 HALFCLK OSDIEN DENDIF 0 OSDD3 OSDD2 OSDD1 OSDD0 OSDD10 OSDD9 OSDD8 R = Reserved MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 55
... Reset: Read: MMRXIF Multi-Master IIC $006D Status Register Write: (MMSR) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 15) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit COLA4 DOT15 DOT14 DOT13 DOT12 Unaffected by reset IICDATE IICSCLE DDCDATE DDCSCLE HOUTE 0 0 ...
Page 56
... MMRD1 MMRD0 0PWM0 0BRM2 0BRM1 0BRM0 1PWM0 1BRM2 1BRM1 1BRM0 2PWM0 2BRM2 2BRM1 2BRM0 3PWM0 3BRM2 3BRM1 3BRM0 4PWM0 4BRM2 4BRM1 4BRM0 5PWM0 5BRM2 5BRM1 5BRM0 6PWM0 6BRM2 6BRM1 6BRM0 7PWM0 7BRM2 7BRM1 7BRM0 Reserved MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 57
... Unimplemented Write: Reset: Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Note: Writing a logic 0 clears SBSW Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 13 of 15) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit PWM7E PWM6E PWM5E PWM4E Indeterminate = Unimplemented ...
Page 58
... IF5 IF4 IF3 IF14 IF13 IF12 IF11 BPR7 BPR6 BPR5 BPR4 Unimplemented Memory Map Bit 0 ILAD USB IF2 IF1 IF10 IF9 IF8 IF7 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 HVEN1 MASS1 ERASE1 PGM1 Reserved MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 59
... Read: Break Status and Control $FE0E Register Write: (BRKSCR) Reset: Read: COP Control Register $FFFF Write: (COPCTL) Reset Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 15 of 15) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit BPR17 BPR16 BPR15 BPR14 Bit Bit 7 ...
Page 60
... IF2 $FFF9 USB Vector (Low) $FFFA IRQ Vector (High) IF1 $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) — $FFFD SWI Vector (Low) $FFFE Reset Vector (High) — $FFFF Reset Vector (Low) MC68HC908LD64 Memory Map Vector Rev. 3.0 — Freescale Semiconductor ...
Page 61
... RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Random-Access Memory (RAM) 18.6 OSD Screen Memory Data Sheet 61 ...
Page 62
... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Data Sheet 62 Random-Access Memory (RAM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 63
... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Section 4. FLASH Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 FLASH Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 OSD FLASH Even High Byte Write Buffer (OSDEHBUF FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 68 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 69 FLASH Program Operation .70 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 FLASH Block Protect Registers ...
Page 64
... BPR5 BPR4 BPR17 BPR16 BPR15 BPR14 DOT15 DOT14 DOT13 DOT12 Unaffected by reset FLASH Memory Bit 0 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 HVEN1 MASS1 ERASE1 PGM1 BPR13 BPR12 BPR11 DOT11 DOT10 DOT9 DOT8 Table 4-1. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 65
... A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor 13,312 Array 1,024 12,288 $0C00–$0FFF $1000–$3FFF ...
Page 66
... High voltage enabled to array and charge pump High voltage disabled to array and charge pump off Data Sheet 66 $FE07 Bit Unimplemented $FE0A Bit Unimplemented (OSDEHBUF). FLASH Memory Bit 0 HVEN MASS ERASE PGM Bit 0 HVEN1 MASS1 ERASE1 PGM1 4.4.1 OSD FLASH Even MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 67
... Reset has no effect on these bits. See map. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor 1 = Mass Erase operation selected 0 = Mass Erase operation not selected 1 = Erase operation selected 0 = Erase operation not selected 1 = Program operation selected 0 = Program operation not selected ...
Page 68
... While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Data Sheet 68 (min. 5µs) nvs (min. 10ms) Erase (min. 5µs) nvh (min. 1µs), the memory can be accessed again in rcv MC68HC908LD64 FLASH Memory Rev. 3.0 — Freescale Semiconductor ...
Page 69
... FLASH array that is being programmed or erased. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor register. address range. (5µs). nvs (10ms). ERASE (100µ ...
Page 70
... FLASH address to be programmed. (min. 20µs). PROG (min. 5µs). nvh (min 1µs), the memory can be accessed in read rcv maximum. See 24.14 FLASH Memory PROG MC68HC908LD64 FLASH Memory Rev. 3.0 — Freescale Semiconductor ...
Page 71
... PROG This row program algorithm assumes the row programmed are initially erased. Figure 4-5. FLASH Programming Flowchart MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor 1 Set PGM bit 2 Write any data to any FLASH address within the row address range desired 3 Wait for a time, t ...
Page 72
... Reset: Figure 4-7. 13K-byte FLASH Block Protect Register 1 (FLBPR1) Data Sheet 72 $FE08 Bit BPR7 BPR6 BPR5 BPR4 $FE0B Bit BPR17 BPR16 BPR15 BPR14 FLASH Memory Bit 0 0 BPR3 BPR2 BPR1 Bit 0 0 BPR13 BPR12 BPR11 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 73
... Start address of FLASH block protect Examples of block protection for 47,616-byte FLASH memory array: and so on... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Figure 4-8. FLASH Block Protect Start Address BPR[7:0] $40 The entire 47,616 bytes of FLASH memory is protected. $42 (0100 0010) $4200 (0100 0010 0000 0000) to $FFFF ...
Page 74
... The entire 13K-byte FLASH memory is not protected. FLASH Memory MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 75
... MCU recommended that this register be written immediately after reset. The configuration register is located at $001F. The configuration register may be read at anytime. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Stop mode recovery time (32 OSCXCLK cycles or 4096 OSCXCLK cycles) ...
Page 76
... Operating Properly 1 = COP module disabled 0 = COP module enabled Data Sheet 76 $001F Bit Unimplemented Figure 5-1. Configuration Register (CONFIG) 13 – – 2 (COP).) Configuration Register (CONFIG Bit 0 SSREC COPRS STOP COPD (COP).) 4 OSCXCLK cycles 4 OSCXCLK cycles Section 22. Computer MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 77
... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Stop Mode ...
Page 78
... Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64-Kbytes • Low-power stop and wait modes Data Sheet 78 Central Processor Unit (CPU) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 79
... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor shows the five CPU registers. CPU registers are not part Figure 6-1. CPU Registers ...
Page 80
... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Read: Write: Reset: Data Sheet 80 Bit Indeterminate Figure 6-3. Index Register (H:X) Bit Figure 6-4. Stack Pointer (SP) Central Processor Unit (CPU) Bit Bit MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 81
... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Read: Write: Reset: MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit Loaded with Vector from $FFFE and $FFFF Figure 6-5 ...
Page 82
... The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Data Sheet 82 Bit Indeterminate Figure 6-6. Condition Code Register (CCR) Central Processor Unit (CPU Bit MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 83
... Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result ...
Page 84
... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock. Data Sheet 84 Central Processor Unit (CPU) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 85
... The opcode map is provided in MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock. ...
Page 86
... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 87
... Branch if Interrupt Mask Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? (N ⊕ ← (PC rel ? ( ⊕ ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← ...
Page 88
... DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 89
... Exclusive OR M with A EOR opr,X EOR ,X EOR opr,SP EOR opr,SP MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Description (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – ...
Page 90
... SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 44 1 INH 54 1 IX1 SP1 9E64 ff 5 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 91
... Rotate Right through Carry ROR opr,X ROR ,X ROR opr,SP RSP Reset Stack Pointer MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← ...
Page 92
... SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 SP2 9ED0 ee ff MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 93
... Indexed, 16-bit offset addressing mode M Memory location N Negative bit MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Description PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 94
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 ...
Page 95
... The MC68HC908LD64 operates from a nominal 24MHz crystal or external clock, providing an 8MHz internal bus clock. The 24MHz clock is required for various modules, such as the CGM and USB. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Section 7. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .96 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Crystal Amplifier Input Pin (OSC1 Crystal Amplifier Output Pin (OSC2) ...
Page 96
... Pierce S To SIM OSCXCLK OSC1 OSC2 can be zero (shorted) when used with S higher-frequency crystals. Refer to manufacturer’s data 24MHz Figure 7-1. Oscillator External Connections Oscillator (OSC) 7-1. This figure shows only To SIM OSCOUT ÷ 2 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 97
... SIM and results in the internal bus frequency being one fourth of the OSCXCLK frequency. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ) and comes directly from the crystal oscillator circuit. XCLK shows only the logical relation of OSCXCLK to OSC1 and Oscillator (OSC) Oscillator (OSC) ...
Page 98
... SIM module. 7.5.2 Stop Mode The STOP instruction disables the OSCXCLK output. 7.6 Oscillator During Break Mode The oscillator continues drive OSCXCLK when the chip enters the break state. Data Sheet 98 MC68HC908LD64 Oscillator (OSC) Rev. 3.0 — Freescale Semiconductor ...
Page 99
... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .103 CGM I/O Signals 103 External Filter Capacitor Pin (CGMXFC 103 PLL Analog Power Pin (VDDA 103 PLL Analog Ground Pin (VSSA 103 Crystal Output Frequency Signal (OSCXCLK) ...
Page 100
... Base clock selector circuit; this software-controlled circuit selects either OSCXCLK divided by two or the VCO clock CGMVCLK divided by two, as the base clock DCLK1. The sync processor derives other display clocks from DCLK1. Data Sheet 100 Clock Generator Module (CGM) Section 7. Oscillator MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 101
... Section 7. Oscillator OSC2 OSC1 SIMOSCEN (FROM SIM) PHASE-LOCKED LOOP (PLL) HVOCR[1:0] CGMRDV REFERENCE PHASE DETECTOR LOCK DETECTOR LOCK CGMVDV MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor (OSC).) ÷ 2 OSCRCLK DIVIDER BCS V CGMXFC V DDA SSA VRS[7:4] VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG ...
Page 102
... Bit VRS7 VRS6 VRS5 VRS4 HVOCR1 HVOCR0 Reserved Video Modes DCLK DE Video Mode Frequency VGA 640 × 480 24MHz SVGA 800 × 600 40MHz XGA 1024 × 768 64MHz SXGA 1280 × 1024 108MHz MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 103
... VSS pin. NOTE: Route VDDA and VSSA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor (OSC).) should be placed as close to the F F Clock Generator Module (CGM) Clock Generator Module (CGM) CGM I/O Signals Section 7 ...
Page 104
... PLL programming register (PPG) • H & V sync output control register (HVOCR) Data Sheet 104 ) and is generated directly from the crystal oscillator XCLK ) and provides the reference for the PLL circuit. XCLK Clock Generator Module (CGM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 105
... PLL control register. Reset clears the PLLF bit. NOTE: The PLLF bit should not be inadvertently cleared. Any read or read- modify-write operation on the PLL control register clears the PLLF bit. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor $0038 Bit PLLF PLLIE PLLON ...
Page 106
... Indicates when the PLL is locked • In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode • In manual operation, forces the PLL into acquisition or tracking mode Data Sheet 106 Clock Generator Module (CGM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 107
... PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor $0039 Bit LOCK AUTO ACQ ...
Page 108
... VCO. Address: Read: Write: Reset: Data Sheet 108 $003A Bit MUL7 MUL6 MUL5 MUL4 Figure 8-5. PLL Programming Register (PPG) Clock Generator Module (CGM Bit 0 VRS7 VRS6 VRS5 VRS4 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 109
... VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming may result in failure of the PLL to achieve lock. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Table 8-2. VCO Frequency Multiplier (N) Selection MUL7:MUL6:MUL5:MUL4 0000 0001 0010 ...
Page 110
... Clock Generator Module (CGM Bit 0 R HVOCR1 HVOCR0 Reserved Video Modes DCLK DE Video Mode Frequency VGA 640 × 480 24MHz SVGA 800 × 600 40MHz XGA 1024 × 768 64MHz SXGA 1280 × 1024 108MHz MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 111
... PLL without turning it off. Applications that require the PLL to wake the MCU from WAIT mode also can deselect the PLL output without turning off the PLL. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Clock Generator Module (CGM) Clock Generator Module (CGM) Interrupts Data Sheet 111 ...
Page 112
... With BCFE at 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Data Sheet 112 Section 9. System Integration (SIM). Clock Generator Module (CGM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 113
... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 117 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . 117 Reset and System Initialization 118 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Active Resets from Internal Sources ...
Page 114
... SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SIM Break Status Register (SBSR 134 SIM Reset Status Register (SRSR 135 SIM Break Flag Control Register (SBFCR 136 9-1. Figure 9-2 shows a summary of the SIM I/O registers. The System Integration Module (SIM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 115
... RESET PIN LOGIC SIM RESET STATUS REGISTER MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET RESET PIN CONTROL CONTROL RESET INTERRUPT CONTROL AND PRIORITY DECODE Figure 9-1. SIM Block Diagram ...
Page 116
... Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal System Integration Module (SIM Bit 0 SBSW Note 0 ILAD USB IF2 IF1 IF10 IF9 IF8 IF7 Reserved MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 117
... OSCXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 OSCXCLK cycles. (See Mode.) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor OSCXCLK OSCOUT ÷ 2 OSCILLATOR OSC2 Figure 9-3. OSC Clock Signals ...
Page 118
... Data Sheet 118 Table 9-2. PIN Bit Set Table 9-2. PIN Bit Set Timing Number of Cycles Required to Set PIN POR 4163 (4096 + System Integration Module (SIM) 9.5 SIM Counter), but an 9.8 SIM Registers). Timing). Figure 9 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 119
... The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. OSCXCLK MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor RST IAB PC Figure 9-4. External Reset Timing Timing). An internal reset can be caused by an illegal Reset). Note that for POR resets, the SIM cycles through Figure 9-5 ...
Page 120
... The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. OSC1 PORRST OSCXCLK OSCOUT RST IAB Data Sheet 120 4096 32 32 CYCLES CYCLES CYCLES Figure 9-7. POR Recovery System Integration Module (SIM) $FFFE $FFFF MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 121
... The SIM actively pulls down the RST pin for all internal reset sources. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor 4 – 2 OSCXCLK cycles, drives the COP counter. The COP should be System Integration Module (SIM) System Integration Module (SIM) ...
Page 122
... OSCXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared. Data Sheet 122 System Integration Module (SIM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 123
... Normally, sequential program execution can be changed in three different ways: • • • MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor for counter control and internal reset Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) Reset Break interrupts System Integration Module (SIM) ...
Page 124
... SP – 4 VECT CCR . Figure 9-8 Interrupt Entry SP – – – 1[15:8] PC – 1[7:0] Figure 9-9. Interrupt Recovery System Integration Module (SIM) flow charts the handling of Figure VECT L START ADDR V DATA H V DATA L OPCODE OPCODE OPERAND MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 125
... YES (As many interrupts as exist on chip) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO YES USB INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. YES SWI INSTRUCTION? NO YES RTI INSTRUCTION? NO Figure 9-10. Interrupt Processing ...
Page 126
... Data Sheet 126 Processing.) CLI LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Figure 9-11 Interrupt Recognition Example System Integration Module (SIM) Figure Figure 9-11 BACKGROUND ROUTINE MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 127
... The interrupt status registers can be useful for debugging. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Table 9-3 summarizes the interrupt sources and the interrupt System Integration Module (SIM) System Integration Module (SIM) Exception Control Data Sheet ...
Page 128
... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 129
... Bit 1 and Bit 0 — Always read 0 9.6.2.2 Interrupt Status Register 2 Address: Read: Write: Reset: IF14–IF7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor $FE04 Bit IF6 IF5 IF4 ...
Page 130
... Upon leaving break mode, execution of the second step will clear the flag as normal. Data Sheet 130 (BRK)). The SIM puts the CPU into the System Integration Module (SIM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 131
... Figure 9-15 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Figure 9-14 shows the timing for wait mode entry. IAB WAIT ADDR WAIT ADDR + 1 IDB ...
Page 132
... IDB $A6 $A6 $A6 $01 Figure 9-15. Wait Recovery from Interrupt or Break 32 Cycles $6E0B $A6 $A6 $A6 Figure 9-16. Wait Recovery from Internal Reset System Integration Module (SIM) $00FF $00FE $00FD $00FC $0B $6E 32 Cycles RST VCT H RST VCT L MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 133
... NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. OSCXCLK INT/BREAK IAB Figure 9-18. Stop Mode Recovery from Interrupt or Break MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Figure 9-17 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA R/W Figure 9-17 ...
Page 134
... Table 9-4. SIM Registers Summary Address Register $FE00 SBSR $FE01 SRSR $FE03 SBFCR $FE00 Bit Reserved Figure 9-19. SIM Break Status Register (SBSR) System Integration Module (SIM) Table 9-4 shows the Access Mode User User User Bit 0 SBSW Note 0 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 135
... Read: Write: POR: POR — Power-On Reset Bit PIN — External Reset Bit MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ; See if wait mode or stop mode was exited by ; break. ;If RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ...
Page 136
... MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Data Sheet 136 $FE03 Bit BCFE Reserved System Integration Module (SIM Bit MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 137
... V vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Section 10. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Data Format ...
Page 138
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 138 1 Figure 10-1 shows a sample circuit used to enter monitor Monitor ROM (MON reset vector is TST , is applied to TST MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 139
... SW2: Position D — For monitor mode entry when reset vector is blank ($FFFE and $FFFF = $FF): Bus clock = OSCXCLK ÷ 4; PTC0, PTC1, and PTC3 voltages are not required. 3. See Table 24-4 for IRQ voltage level requirements. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor V TST 10 Ω SW2 C (See NOTES) D ...
Page 140
... The break signal also provides a timing reference to allow the host to determine the necessary baud rate. Data Sheet 140 shows the pin conditions for entering monitor mode. As 9.8304 MHz with PTC3 high Monitor ROM (MON) ) TST Table 10-1 after MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 141
Table 10-1. Monitor Mode Signal Requirements and Options Address IRQ RST $FFFE/ PTC3 PTC1 $FFFF X GND TST TST TST TST ...
Page 142
... Disabled ) is removed from the IRQ pin, the SIM asserts its COP enable TST Figure 10-2 Monitor ROM (MON) is applied TST SWI SWI Vector Vector High Low $FFFC $FFFD $FEFC $FEFD and Figure 10-3.) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 143
... A start bit followed by nine low bits is a break signal (see Figure 10-5). When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor BIT 0 BIT 1 BIT 2 BIT 3 BIT Figure 10-2 ...
Page 144
... Read byte from memory Specifies 2-byte address in high byte:low byte order Data Returns contents of specified address $4A Command Sequence ADDRESS ADDRESS ADDRESS READ HIGH HIGH LOW Monitor ROM (MON) TWO-STOP-BIT DELAY BEFORE ZERO ECHO ADDRESS DATA LOW RETURN MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 145
... Description Operand Returned ECHO Description Operand Returned MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Table 10-4. WRITE (Write Memory) Command Write byte to memory Specifies 2-byte address in high byte:low byte order; low byte followed by data byte Data None Opcode $49 Command Sequence SENT TO MONITOR ...
Page 146
... IWRITE ECHO Table 10-7. READSP (Read Stack Pointer) Command Reads stack pointer None Returns stack pointer in high byte:low byte order $0C Command Sequence SENT TO MONITOR READSP READSP ECHO Monitor ROM (MON) DATA SP SP HIGH LOW RETURN MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 147
... PTC3 pin upon entry into monitor mode. When PTC3 is high, the divide by ratio is 1024. If the PTC3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Table 10-8. RUN (Run User Program) Command Executes RTI instruction None Data None ...
Page 148
... Monitor ROM (MON) Data Sheet 148 Monitor ROM (MON) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 149
... TIM Counter Modulo Registers (TMODH:TMODL 164 11.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) . 165 11.10.5 TIM Channel Registers (TCH0H/L:TCH1H/ 168 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Section 11. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 TIM Counter Prescaler ...
Page 150
... The TIM shares the TCH0 pin with the sync processor CLAMP output. Data Sheet 150 is a block diagram of the TIM. Table 11-1. Pin Name Conventions TIM Generic Pin Name: Full TIM Pin Name: Pin Selected for TCH0 By: Timer Interface Module (TIM) TCH0 CLAMP/TCH0 ELS0B:ELS0A MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 151
... COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor shows the structure of the TIM. The central component of PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A ...
Page 152
... PS2 PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 153
... When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Bit Bit15 Bit14 ...
Page 154
... Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. Data Sheet 154 11.5.3 Output Compare. The pulses are Timer Interface Module (TIM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 155
... Program the TIM to set the pin if the state of the PWM pulse is logic zero. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Figure 11-2 shows, the output compare value in the TIM channel Timer Interface Module (TIM) Timer Interface Module (TIM) Functional Description ...
Page 156
... WIDTH OUTPUT COMPARE Figure 11-2. PWM Period and Pulse Width (see 11.10.1 TIM Status and Control Register 11.5.4 Pulse Width Modulation Timer Interface Module (TIM) OVERFLOW OUTPUT OUTPUT COMPARE COMPARE (TSC)). (PWM). The pulses are MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 157
... I/O pin. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value ...
Page 158
... Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Timer Interface Module (TIM) Table 11-3.) Table 11-3.) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 159
... TIM before executing the WAIT instruction. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor (TSC0:TSC1). TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests ...
Page 160
... CLAMP output signal. TCH0 pin is programmable independently as an input capture pin or an output compare pin. It also can be configured as a buffered output compare or buffered PWM pin. Data Sheet 160 23.6.4 SIM Break Flag Control Timer Interface Module (TIM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 161
... TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) ...
Page 162
... PS[2:0] — Prescaler Select Bits These read/write bits select either the TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as shows. Reset clears the PS[2:0] bits. Data Sheet 162 Timer Interface Module (TIM) Table 11-2 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 163
... TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. Address: Read: Write: Reset: Address: Read: Write: Reset: MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Table 11-2. Prescaler Selection PS1 PS0 ...
Page 164
... Reset the TIM counter before writing to the TIM counter modulo registers. Data Sheet 164 $000E TMODH Bit Bit15 Bit14 Bit13 Bit12 $000F TMODL Bit Bit7 Bit6 Bit5 Bit4 Timer Interface Module (TIM Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 165
... When channel x is MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare ...
Page 166
... When ELSxB:A = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See 1 = Initial output level low 0 = Initial output level high Data Sheet 166 Table 11-3. Table 11-3.) Reset clears the MSxA bit. Timer Interface Module (TIM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 167
... Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor shows how ELSxB and ELSxA work. Reset clears the Table 11-3. Mode, Edge, and Level Selection MSxA ELSxB ...
Page 168
... Data Sheet 168 shows, the CHxMAX bit takes effect in the cycle after it OVERFLOW OVERFLOW OVERFLOW PERIOD OUTPUT OUTPUT COMPARE COMPARE Figure 11-7. CHxMAX Latency Timer Interface Module (TIM) OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 169
... Address: Read: Write: Reset: Address: Read: Write: Reset: Address: Read: Write: Reset: Address: Read: Write: Reset: MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor $0011 TCH0H Bit Bit15 Bit14 Bit13 Indeterminate after reset $0012 TCH0L Bit Bit7 Bit6 Bit5 Indeterminate after reset $0014 ...
Page 170
... Timer Interface Module (TIM) Data Sheet 170 Timer Interface Module (TIM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 171
... The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. Example of the waveforms are shown in MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 PWM Registers 173 PWM Data Registers (0PWM–7PWM 173 PWM Control Register (PWMCR 174 ...
Page 172
... PWM3E PWM2E PWM1E PWM0E MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 173
... The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. Examples of PWM output waveforms are shown in Figure MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor PWM data registers ($0070–$0077) PWM control register ($0078) $0070–$0077 Bit ...
Page 174
... PTB0 PWM0 PTB1 PWM1 PTB2 PWM2 PTB3 PWM3 PTB4 PWM4 PTB5 PWM5 PTB6 PWM6 PTB7 PWM7 Pulse Width Modulator (PWM Bit 0 PWM3E PWM2E PWM1E PWM0E Control Bit PWM0E PWM1E PWM2E PWM3E PWM4E PWM5E PWM6E PWM7E MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 175
... N = value set in 3-bit BRM (bit0-bit2) N xx1 x1x 1xx Figure 12-4. 8-Bit PWM Output Waveforms MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor 1 PWM cycle = 32T 31T 16T 31T Pulse inserted at end of PWM cycle depends on setting of N. PWM cycles where pulses are Number of inserted pulses in ...
Page 176
... Pulse Width Modulator (PWM) Data Sheet 176 Pulse Width Modulator (PWM) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 177
... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Interrupts .181 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Wait Mode ...
Page 178
... Figure 13-1. ADC I/O Register Summary Data Sheet 178 Bit AIEN ADCO ADCH4 AD7 AD6 AD5 AD4 Indeterminate after reset 0 ADIV2 ADIV1 ADIV0 Unimplemented Analog-to-Digital Converter (ADC Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 179
... WRITE DDRC WRITE PTC READ PTC CONVERSION COMPLETE INTERRUPT LOGIC AIEN COCO BUS CLOCK MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Figure 13-2 DDRCx RESET PTCx ADC DATA REGISTER ADC VOLTAGE IN ADCVIN ADC ADC CLOCK CLOCK GENERATOR ADIV[2:0] Figure 13-2. ADC Block Diagram ...
Page 180
... With a 1MHz ADC internal clock the maximum sample rate is 62.5kHz. Data Sheet 180 16 to17 ADC cycles Conversion time = Number of bus cycles = conversion time × bus frequency Analog-to-Digital Converter (ADC) ADC frequency MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 181
... If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to logic 1’s before executing the WAIT instruction. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Table 2-1 . Vector Addresses. Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC) Interrupts ...
Page 182
... ADC Voltage Reference Low Pin (VRL) VRL is the low voltage reference for the ADC. 13.7.5 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the six ADC channels to the ADC module. Data Sheet 182 Analog-to-Digital Converter (ADC) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 183
... The interrupt signal is cleared when the data register is read or the status and control register is written. Reset clears the AIEN bit. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ADC status and control register (ADSCR) ADC data register (ADR) ADC input clock register (ADICLK) $003B Bit 7 ...
Page 184
... ADC1 1 0 ADC2 1 1 ADC3 0 0 ADC4 0 1 ADC5 1 0 ↓ ↓ Analog-to-Digital Converter (ADC) Input Select PTC0/ADC0 PTC1/ADC1 PTC2/ADC2 PTC3/ADC3 PTC4/ADC4 PTC5/ADC5 (1) — Unused — Reserved — Unused VRH VRL ADC power off MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 185
... ADIV[2:0] — ADC Clock Prescaler Bits ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. available clock configurations. The ADC clock should be set to approximately 1MHz. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor $003C Bit AD7 AD6 ...
Page 186
... Table 13-2. ADC Clock Divide Ratio ADIV1 ADIV0 Analog-to-Digital Converter (ADC) ADC Clock Rate ADC Input Clock ÷ 1 ADC Input Clock ÷ 2 ADC Input Clock ÷ 4 ADC Input Clock ÷ 8 ADC Input Clock ÷ 16 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 187
... MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Overview .192 Hub Function I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 194 USB Hub Root Port Control Register (HRPCR 194 USB Hub Downstream Port Control Registers (HDP1CR–HDP4CR 195 USB SIE Timing Interrupt Register (SIETIR) ...
Page 188
... Hub interrupt endpoint 1 – 1-byte transmit buffer • USB interrupts – Transaction interrupt driven – Start of frame interrupt Data Sheet 188 Universal Serial Bus Module (USB) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 189
... The full name of the USB I/O pins are listed in generic pin name appear in the text that follows. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor – EOF2 interrupt – End of packet interrupt – Signal transition interrupt – Frame timer locked interrupt Hub repeater and controller function – ...
Page 190
... USBDS3E bit in PECR ($0068) USBDS4E bit in PECR ($0068 Bit 0 DE0Rx3 DE0Rx2 DE0Rx1 DE0Rx0 DE0Tx3 DE0Tx2 DE0Tx1 DE0Tx0 DE1Tx3 DE1Tx2 DE1Tx1 DE1Tx0 HE0Rx3 HE0Rx2 HE0Rx1 HE0Rx0 HE0Tx3 HE0Tx2 HE0Tx1 HE0Tx0 ENABLE2 ENABLE1 DSTALL2 DSTALL1 DADD3 DADD2 DADD1 DADD0 MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 191
... Reset: Read: USB SIE Timing Interrupt $0056 Register Write: (SIETIR) Reset: Read: USB SIE Timing Status $0057 Register Write: (SIETSR) Reset: Figure 14-1. USB I/O Register Summary MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor RXD0F T0SEQ DSTALL0 TX0E RX0E T1SEQ ENDADD ...
Page 192
... RSEQ SETUP TX1ST 0 TX1STR RESUM0 SUSPND Unimplemented Universal Serial Bus Module (USB) ADD3 ADD2 ADD1 ADD0 TXDIE RXDIE TXDFR RXDFR TPSIZ3 TPSIZ2 TPSIZ1 TPSIZ0 PCHG3 PCHG2 PCHG1 PCHG0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0 D0+ D0– MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 193
... ENDPOINT) 8-BYTE TRANSMIT BUFFER 12MHz OSCOUT FROM OSC D4+ D4– Figure 14-2. USB Module Block Diagram MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor CPU BUS ENDPOINT 0 (CONTROL ENDPOINT) REGISTERS 8-BYTE TRANSMIT BUFFER 8-BYTE RECEIVE BUFFER ENDPOINT 1 (INTERRUPT ENDPOINT) 8-BYTE TRANSMIT BUFFER ...
Page 194
... When the global resume or the downstream remote wakeup signal is found by the suspended hub, Data Sheet 194 $005E Bit RESUM0 SUSPND Indeterminate = Unimplemented Universal Serial Bus Module (USB Bit 0 0 D0+ D0– MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 195
... Setting this bit to 1 enables the port; clearing this bit to 0 disables the port. In the enabled state a full-speed port propagates all downstream signaling; MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor $0051–$0054 HRP1CR–HRP4CR Bit PEN1 ...
Page 196
... Downstream selective resume sequence to a port may also be initiated via the host request ClearPortFeature (PORT_SUSPEND). Software should control the timing of the forced resume signaling downstream for at least 20ms. Data Sheet 196 Universal Serial Bus Module (USB) MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 197
... SUSPND bit is 1, the data reflects the current state on the data line while accessing this register. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor 1 = Force downstream port data lines to K state 0 = Default 1 = Force downstream port enters the selective suspend mode 0 = Default Universal Serial Bus Module (USB) ...
Page 198
... Writing to EOPF has no effect End-of-Packet sequence has been detected 0 = End-of-Packet sequence has not been detected Data Sheet 198 $0056 Bit SOFF EOF2F EOPF TRANF Unimplemented Universal Serial Bus Module (USB Bit 0 SOFIE EOF2IE EOPIE TRANIE MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...
Page 199
... This read/write bit enables the bus signal transition to generate a USB interrupt when the TRANF bit becomes set. Reset clears this bit. MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor 1 = Signal transition has been detected 0 = Signal transition has not been detected 1 = USB interrupt enabled for Start Of Frame 0 = USB interrupt disabled for Start Of Frame ...
Page 200
... Writing a logic 1 to this write-only bit will clear the LOCKF bit set. Reset clears this bit Write 1 to clear the LOCKF bit effect Data Sheet 200 $0057 Bit RSTF 0 LOCKF 0 RSTFR LOCKFR Unimplemented Universal Serial Bus Module (USB Bit SOFFR EOF2FR EOPFR TRANFR MC68HC908LD64 Rev. 3.0 — Freescale Semiconductor ...