MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 277

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.7 OSD Module I/O Registers
18.7.1 OSD Control Register (OSDCR)
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Address:
Seven registers are associated with the OSD module, they outlined in
the following sections.
OSDMEN — OSD Memory Enable
OSDRST — OSD Module Reset
CLKINV — Pixel Clock Inversion
Reset:
Read:
Write:
When this bit is clear, the OSD RAM and font FLASH memory is
directly under CPU access. When OSDMEN is set, OSD circuitry has
read control over the OSD RAM and font FLASH memory for
displaying the contents; CPU access is indirect, by writing to address
and data buffers. The OSDMEN bit should be cleared while no OSD
are displaying. Reset clear this bit.
Setting this bit resets the entire OSD logic and row15 registers (row1
to row14 registers are unaffected), and holds the OSD in the reset
state. The input PCLK clock is prevented from entering the OSD
module to reduce power consumption.
Reset clear this bit.
This bit is set to invert the PCLK input of OSD. Reset clears this bit.
1 = OSD RAM and font FLASH is under OSD circuitry access
0 = OSD RAM and font FLASH is directly under CPU access
1 = Reset OSD logic and row15 registers
0 = No effect
1 = PCLK input inverted
0 = PCLK input not inverted
OSDMEN
$0060
Bit 7
0
Figure 18-5. OSD Control Register (OSDCR)
On-Screen Display (OSD)
R
6
OSDRST
5
0
CLKINV
4
0
CLKPH1
3
0
CLKPH0 HALFCLK OSDIEN
OSD Module I/O Registers
On-Screen Display (OSD)
2
0
1
0
Data Sheet
0
0
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