MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 261

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.6.2 Sync Processor Input/Output Control Register (SPIOCR)
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Figure 17-5. Sync Processor Input/Output Control Register (SPIOCR)
Address:
VPOL — Vsync Input Polarity
HPOL — Hsync Input Polarity
VSYNCS — VSYNC Input State
HSYNCS — HSYNC Input State
Reset:
Read: VSYNCS HSYNCS
Write:
This bit indicates the polarity of the VSYNC input, or the extracted
Vsync from a composite sync input (COMP=1). Reset clears this bit.
This bit indicates the polarity of the HSYNC input. This bit equals the
VPOL bit when the COMP bit is set. Reset clears this bit.
This read-only bit reflects the logical state of the VSYNC input.
This read-only bit reflects the logical state of the HSYNC input.
ATPOL
1 = Vsync is positive polarity
0 = Vsync is negative polarity
1 = Hsync is positive polarity
0 = Hsync is negative polarity
0
0
1
1
$0045
Bit 7
0
Table 17-4. ATPOL, VINVO, and HINVO setting
= Unimplemented
Sync Processor
6
0
VINVO / HINVO
COINV
0
1
0
1
5
0
R
4
Same polarity as sync input
Inverted polarity of sync input
Negative polarity sync output
Positive polarity sync output
R
R
3
Sync Outputs:
Sync Processor I/O Registers
VOUT/HOUT
= Reserved
R
2
BPOR
Sync Processor
1
0
Data Sheet
SOUT
Bit 0
0
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