MCF5485CVR200 Freescale Semiconductor, MCF5485CVR200 Datasheet - Page 11

• Manufacturer Part Number: MCF5485CVR200
• Description: IC MPU 32BIT COLDF 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF548xr

Specifications of MCF5485CVR200

• Core Processor: Coldfire V4E
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 99
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MCF548x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 83 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M5485EVBE, M5485EVBGHSE, M5484LITEKITE
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 64KB
• Cpu Speed: 200MHz
• Embedded Interface Type: I2C, UART, DMA
• Digital Ic Case Style: BGA
• No. Of Pins: 388
• Rohs Compliant: Yes
• For Use With: M5485EVBGHSE - KIT DEV GHS FOR M5485EVBM5485EVBGHS - KIT DEV GHS FOR M5485EVBM5485BFEE - MODULE MCF5485 FIRE ENGINEM5485AFEE - MODULE MCF5485 FIRE ENGINEM5485AFE - MODULE MCF5485 FIRE ENGINEM5484GFEE - MODULE M5484 FIRE ENGINEM5484LITEKITE - KIT DEV FOR MCF548X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6
The specifications in
Table 8
Figure 9
Freescale Semiconductor
25.0
25 40 50 60 70
1
2
25.0
AD[12:8]
CLKIN
CLKIN (MHz)
All other values of AD[12:8] are reserved.
DDR memories typically have a minimum speed of 83 MHz. Some vendors specifiy down to 75 MHz. Check with the
memory component specifications to verify.
shows the supported PLL encodings.
00011
00101
01111
correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.
PLL Timing Specifications
50.0
1
Table 7
Num
Clock
Ratio
C1
C2
C3
C4
CLKIN
1:2
1:2
1:4
4x
2x
Cycle time
Rise time (20% of Vdd to 80% of vdd)
Fall time (80% of Vdd to 20% of Vdd)
Duty cycle (at 50% of Vdd)
30
are for the CLKIN pin.
CLKIN—PCI and FlexBus
Figure 9. CLKIN, Internal Bus, and Core Clock Ratios
40 50 60 70 80 90 100
Frequency Range (MHz)
Internal Clock (MHz)
50.0
Table 8. MCF548x Divide Ratio Encodings
Internal Clock
41.67–50.0
25.0–41.67
Characteristic
MCF548x ColdFire
Figure 8. Input Clock Timing Diagram
Table 7. Clock Timing Specifications
25.0
C4
C1
100.0
100.0
C4
®
Microprocessor, Rev. 4
Internal XLB, SDRAM Bus,
and PSTCLK Frequency
60
70 80 90 100110120130140150160170180190200
Range (MHz)
50.0–83.33
2x
2x
83.33–100
C3
Min
20
40
—
—
100
100.0
2
Core Clock (MHz)
C2
Max
40
60
2
2
Core Frequency Range
Core Clock
Units
PLL Timing Specifications
ns
ns
ns
%
100.0–166.66
166.66–200
(MHz)
200
200.0
200.0
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