MCF5485CVR200 Freescale Semiconductor, MCF5485CVR200 Datasheet - Page 22

• Manufacturer Part Number: MCF5485CVR200
• Description: IC MPU 32BIT COLDF 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF548xr

Specifications of MCF5485CVR200

• Core Processor: Coldfire V4E
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 99
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MCF548x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 83 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M5485EVBE, M5485EVBGHSE, M5484LITEKITE
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 64KB
• Cpu Speed: 200MHz
• Embedded Interface Type: I2C, UART, DMA
• Digital Ic Case Style: BGA
• No. Of Pins: 388
• Rohs Compliant: Yes
• For Use With: M5485EVBGHSE - KIT DEV GHS FOR M5485EVBM5485EVBGHS - KIT DEV GHS FOR M5485EVBM5485BFEE - MODULE MCF5485 FIRE ENGINEM5485AFEE - MODULE MCF5485 FIRE ENGINEM5485AFE - MODULE MCF5485 FIRE ENGINEM5484GFEE - MODULE M5484 FIRE ENGINEM5484LITEKITE - KIT DEV FOR MCF548X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet AC Timing Specifications
11
11.1
The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing
specs/constraints for the EMAC_10_100 I/O signals.
The following timing specs meet the requirements for MII and 7-Wire style interfaces for a range of transceiver devices. If this
interface is to be used with a specific transceiver device the timing specs may be altered to match that specific transceiver.
22
1
2
3
4
5
6
Num
P10
P11
P12
Please see the reset configuration signals description in the “Signal Descriptions” chapter within the MCF548x
Reference Manual. Also specific guidelines may need to be followed when operating the system PLL below certain
frequencies.
Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals.
PCI 2.2 spec does not require an output hold time. Although the MCF548X may provide a slight amount of hold, it
is not required or guaranteed.
PCI 2.2 spec requires zero input hold.
These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec.
P7
P8
P9
Fast Ethernet AC Timing Specifications
MII/7-WIRE Interface Timing Specs
PCI GNT (0 < PCI ≤ 33Mhz) - Input Setup (t
PCI signals (0–50 Mhz) - Input Hold (t
PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Output valid (t
PCI REQ/GNT (0 < PCI ≤ 33Mhz) - Output valid (t
PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Input Setup (t
PCI REQ (0 < PCI ≤ 33Mhz) - Input Setup (t
Setup/Hold
Valid/Hold
Output
CLKIN
Input
Table 14. PCI Timing Specifications (continued)
MCF548x ColdFire
Characteristic
Figure 18. PCI Timing
P4
IH
)
P1
IS
IS
®
)
)
Microprocessor, Rev. 4
P2
Output Valid
DV
Input Valid
IS
DV
)
)
)
P6
P7
Min
—
—
—
12
10
0
Max
12
—
—
—
6
5
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
Notes
5
6