MCF5485CVR200 Freescale Semiconductor, MCF5485CVR200 Datasheet - Page 13

• Manufacturer Part Number: MCF5485CVR200
• Description: IC MPU 32BIT COLDF 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF548xr

Specifications of MCF5485CVR200

• Core Processor: Coldfire V4E
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 99
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MCF548x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 83 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M5485EVBE, M5485EVBGHSE, M5484LITEKITE
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 64KB
• Cpu Speed: 200MHz
• Embedded Interface Type: I2C, UART, DMA
• Digital Ic Case Style: BGA
• No. Of Pins: 388
• Rohs Compliant: Yes
• For Use With: M5485EVBGHSE - KIT DEV GHS FOR M5485EVBM5485EVBGHS - KIT DEV GHS FOR M5485EVBM5485BFEE - MODULE MCF5485 FIRE ENGINEM5485AFEE - MODULE MCF5485 FIRE ENGINEM5485AFE - MODULE MCF5485 FIRE ENGINEM5484GFEE - MODULE M5484 FIRE ENGINEM5484LITEKITE - KIT DEV FOR MCF548X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.1
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.
Freescale Semiconductor
1
2
3
4
5
Num
FB1
FB2
FB3
FB4
FB5
FB6
FB7
FB8
FB9
The frequency of operation is the same as the PCI frequency of operation. The MCF548X supports a single
external reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI.
Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
Timing for chip selects only applies to the FBCS[5:0] signals. Please see
Characteristics” for SDCS[3:0] timing.
The FlexBus supports programming an extension of the address hold. Please consult the MCF548X
specification manual for more information.
These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address
signals.
FlexBus AC Timing Characteristics
Frequency of Operation
Clock Period (CLKIN)
Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
Data Input Setup
Data Input Hold
Transfer Acknowledge (TA) Input Setup
Transfer Acknowledge (TA) Input Hold
Address Output Valid (PCIAD[31:0])
Address Output Hold (PCIAD[31:0])
Table 10. FlexBus AC Timing Specifications
MCF548x ColdFire
Characteristic
®
Microprocessor, Rev. 4
Section 9.2, “DDR SDRAM AC Timing
Min
3.5
25
20
—
—
1
0
4
0
0
Max
7.0
7.0
50
40
—
—
—
—
—
—
Unit
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
3, 4
1
2
3
5
5
FlexBus
13