MCF5485CVR200 Freescale Semiconductor, MCF5485CVR200 Datasheet - Page 32

• Manufacturer Part Number: MCF5485CVR200
• Description: IC MPU 32BIT COLDF 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF548xr

Specifications of MCF5485CVR200

• Core Processor: Coldfire V4E
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 99
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MCF548x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 83 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M5485EVBE, M5485EVBGHSE, M5484LITEKITE
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 64KB
• Cpu Speed: 200MHz
• Embedded Interface Type: I2C, UART, DMA
• Digital Ic Case Style: BGA
• No. Of Pins: 388
• Rohs Compliant: Yes
• For Use With: M5485EVBGHSE - KIT DEV GHS FOR M5485EVBM5485EVBGHS - KIT DEV GHS FOR M5485EVBM5485BFEE - MODULE MCF5485 FIRE ENGINEM5485AFEE - MODULE MCF5485 FIRE ENGINEM5485AFE - MODULE MCF5485 FIRE ENGINEM5484GFEE - MODULE M5484 FIRE ENGINEM5484LITEKITE - KIT DEV FOR MCF548X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision History
18
32
Revision
Number
2.2
2.3
2.4
Revision History
3
4
December 14, 2005
February 20, 2007
December 4, 2007
August 29, 2005
August 30, 2005
Date
MCF548x ColdFire
Table
spec from 33.3 ns to 40 ns.
Table
Table
Table
and corresponding FB1 minimum from 15.15 ns to 20 ns.
Table
Table
and corresponding FB1 minimum from 15.15 ns to 20 ns.
Table
Table
(33< PCI ≤ 50 Mhz)
Table
Table
Table
Table
Added
Figure
Figure
or PLL VDD by more than 0.4V...” to “IVDD should not exceed EVDD or SD
VDD by more than 0.4V...”
Table
Table
Table
current.
Table
Added features list, pinout drawing, block diagram, and case outline.
7: Changed C1 minimum spec from 15.15 ns to 20 ns and maximum
22: Changed J11 maximum from 15 ns to 20 ns.
9: Changed heading maximum from 66 MHz to 50 MHz.
10: Changed frequency of operation maximum from 66 MHz to 50 MHz
10: Changed FB1 maximum from 33.33 ns to 40 ns.
14: Changed frequency of operation maximum from 66 MHz to 50 MHz
14: Changed FB1 maximum from 33.33 ns to 40 ns.
14: Changed various entry descriptions from “(33 < PCI ≤ 66 Mhz)” to
23: Changed heading maximum from 66 MHz to 50 MHz.
25: Changed heading maximum from 66 MHz to 50 MHz.
4: Updated DC electrical specifications, V
6: Changed FlexBus output load from 20pF to 30pF.
3: Updated thermal information for θ
4: Added input leakage current spec.
6: Added footnote regarding pads having balanced source & sink
9: Added RSTI pulse duration spec.
Section 4.3, “General USB Layout
2: Changed resistor value from 10W to 10Ω
3: Changed note 1 in from “IVDD should not exceed EVDD, SD VDD
®
Microprocessor, Rev. 4
Substantive Changes
Guidelines.”
JMA
, θ
IL
JB
and V
, and θ
IH
Freescale Semiconductor
JC
.