SAB-C167CR-LM HA+ Infineon Technologies, SAB-C167CR-LM HA+ Datasheet - Page 37

• Manufacturer Part Number: SAB-C167CR-LM HA+
• Description: IC MCU 16BIT MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C167CR-LM HA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144- BSQFP
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: 1xUSART, 1xSSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 9
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 16 Channel
• Packages: PG-MQFP-144
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 4.0 KByte
• Can Nodes: 1
• A / D Input Lines (incl. Fadc): 16
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: B167CRLMHAZNP; B167CRLMHAZXP; SAB-C167CR-LMHA; SAB-C167CR-LMHA+; SAB-C167CR-LMHA; SAB-C167CR-LMHAIN; SABC167CRLM-HA; SABC167CRLM-HA; SABC167CRLMHAX; SP000103462

The C167CR also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 5
time:
Table 5
Exception Condition
Reset Functions:
•
•
•
Class A Hardware Traps:
•
•
•
Class B Hardware Traps:
•
•
•
•
•
Reserved
Software Traps
•
Data Sheet
Hardware Reset
Software Reset
W-dog Timer Overflow
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction
Access
Illegal External Bus
Access
TRAP Instruction
shows all of the possible exceptions or error conditions that can arise during run-
Hardware Trap Summary
Trap
Flag
–
NMI
STKOF
STKUF
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
–
–
Trap
Vector
RESET
RESET
RESET
NMITRAP
STOTRAP
STUTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
–
–
35
Vector
Location
00’0000
00’0000
00’0000
00’0008
00’0010
00’0018
00’0028
00’0028
00’0028
00’0028
00’0028
[2C
Any
[00’0000
00’01FC
in steps of
4
H
H
- 3C
H
H
H
H
H
H
H
H
H
H
H
H
H
H
]
Functional Description
-
] [0B
Trap
Number
00
00
00
02
04
06
0A
0A
0A
0A
0A
Any
[00
H
H
H
H
H
H
H
H
H
H
H
H
H
- 7F
- 0F
V3.3, 2005-02
H
H
]
] –
C167CR
C167SR
Trap
Priority
III
III
III
II
II
II
I
I
I
I
I
Current
CPU
Priority