EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 190

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

7
7-8
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7.4.1 VILOSATI (Video Image Line Output Scanner and Transfer
ADR(31:0)
HDAT(31:0)
HADR(31:0)
DAT(31:0)
CGNT
CREQ
The Raster Engine’s video image line output scanner and transfer interface connects to a
either a dedicated DMA port on the SDRAM controller or to AHB access to the SDRAM
controller and reads the video image from SDRAM to the video FIFO. VILOSATI keeps track
of image location, width, and depth for both progressive and dual scanned images. It
responds to controls from the FIFO for more video information. During single scan operation,
when the FIFO level falls below a programmable fill level (FIFOLevel defaults to a value of 16
words), the FULL signal is inactive and VILOSATI attempts to initiate an unspecified length
incrementing burst of at least 16 words. The VILOSATI will initiate incrementing unspecified
length bursts until the FIFO is full. When the FIFO signals that it has emptied below the
FIFOLevel again, the image reading process from the frame buffer continues.
For dual scan operation, the FIFO is split into two halves, where each halve operates with a
separate FULL indicator. In dual scan mode, selected by writing DSCAN = ‘1’ to the
PixelMode
burst of 8 words (the LSB of FIFOLevel is ignored). For dual and single scan displays,
information for the upper left corner of the display begins at the word address stored in the
Note: FIFOLevel values of greater than 16 words are not recommended due to the possibility of
Interface)
Transfer
Interface
Scanner
Address
Output
Image
Cursor
CNTRs
Cursor
Video
Master
AMBA
Line
And
Bus
FIFO underflow.
register, the FULL and DS_FULL indicators trigger when either has room for a
N_CLR
HFULL
ADR
CTR
FULL
Cursor
Machs
IN
N_WR
State
Control
FIFO
RAMs
Logic
32x32
Dual
Two
Port
Cursor
Buffer
Line
N_RD
Figure 7-1. Raster Engine Block Diagram
OUT
ADR
CTR
64
CNTRs
Cursor
Output
Copyright 2007 Cirrus Logic
Pixel
MUX
2
24
Blink
Logic
8
24
256x24
Horizontal
SRAM
Counters
Table
Look
Vertical
Up
and
24
3
Scale
Gray
Gen
Compare
register
logic
and
Color
MUX
24
24
Encoder
Shifting
YCrCb
Logic
Pixel
24
Signature Analyzer
Video Stream
HSYNC/LP
SYNCEN
N/V/CSYNC
BRIGHT
BLANK
DS785UM1
PCLKEN
CCIREN
S/PCLK
DAC
PELEN
To
P[17:0]