EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 663

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

DS785UM1
21.4 I
The following information is required to generate a set of clocks for the I
port i2s_mstr_clk_cfg is used to supply the Syscon block the necessary control information in
2
S Master Clock Generation
Descriptions” on page 448.) Note that both left and right sample registers must be read
for the I
were last read from the FIFO will be put onto the APB bus. The FIFO read pointer is not
updated and stays pointing to the same location. The FIFO underflow flag in the Global
Control Status register is asserted. (See “Register Descriptions” on page 448.) If this
happens to be the first attempted read by the programmer on the FIFO while the FIFO
is still empty, the contents at FIFO location 0 are put onto the APB bus. These contents
are zero if the I
received and the FIFO is full, the new samples are ignored. The existing contents in
FIFO locations 0 to 7 are not touched. An internal Overflow bit is set, marking the FIFO
pointer location at which the last good data was received (that is, at [current FIFO
pointer location - 1]). When the FIFO pointer eventually points at this location again,
after reading all 7 other FIFO locations, the FIFO overflow flag in the Global Control
Status Register is asserted (and an interrupt is asserted, if enabled). The Status
Register bit (and interrupt) is cleared by reading a left / right stereo sample pair from this
FIFO location.
upper bits will be set to zero by the I
registers. Once the new configuration has been set, the channels can be re-enabled
following the specified start order.
has 5 bits per FIFO that reflect the state of the FIFO. They are:
If the programmer attempts to read from the FIFO while it is empty, the contents that
If the I
The data in the FIFO’s is always right justified for word lengths of 16 and 24 bits. The
The I
The status of each FIFO is reflected in the Global Control Status register. This register
• Rx0_underflow - Gets set when the programmer reads the FIFO when it is empty.
• Rx0_overflow - Gets set when an Rx overflow has occurred, and the FIFO pointer is
• Rx0_fifo_empty - Gets set when there are no left and right stereo samples in the
• Rx0_fifo_half_full - Gets set when there are 4 left and right stereo samples or less in
• Rx0_fifo_full - Gets set when there are 8 left and right stereo samples in the FIFO.
pointing at the last FIFO location where data was received before the overflow
occurred
FIFO.
the FIFO.
2
S transmit and receive channels should be disabled before modifying the control
2
S controller signals to the FIFO that new stereo sample pairs have been
2
S controller to consider the location to be free and modify the internal counter.
2
S controller has been reset previously.
Copyright 2007 Cirrus Logic
2
S controller in this case.
2
S controller. The I
EP93xx User’s Guide
I
2
S Controller
21-7
2
S
21