EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 585

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

UART3Flag
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808E_0018 - Read/Write
0x0000_0000
UART3 Flag Register
RSVD:
TXFE:
RXFF:
TXFF:
RXFE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Transmit FIFO Empty. The meaning of this bit depends on
the state of the FEN bit in the UART3LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the transmit
holding register is empty. If the FIFO is enabled, the TXFE
bit is set when the transmit FIFO is empty.
Receive FIFO Full. The meaning of this bit depends on the
state of the FEN bit in the UART3LinCtrlHigh register. If
the FIFO is disabled, this bit is set when the receive
holding register is full. If the FIFO is enabled, the RXFF bit
is set when the receive FIFO is full.
Transmit FIFO Full. The meaning of this bit depends on
the state of the FEN bit in the UART3LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the transmit
holding register is full. If the FIFO is enabled, the TXFF bit
is set when the transmit FIFO is full.
Receive FIFO Empty. The meaning of this bit depends on
the state of the FEN bit in the UART3LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the receive
holding register is empty. If the FIFO is enabled, the RXFE
bit is set when the receive FIFO is empty.
24
8
RSVD
TXFE
23
7
RXFF
22
6
TXFF
21
5
RXFE
20
4
UART3 With HDLC Encoder
BUSY
19
3
EP93xx User’s Guide
DCD
18
2
DSR
17
1
CTS
16
16-9
0
16