EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 803

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

GPIOxIntType2
DS785UM1
31
15
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
The INTTYPE1 register controls what type of INTERRUPT can occur on Port A/B/F. Level
sensitive when “0” is written to a bit location (“0” default on reset), edge sensitive when “1” is
written to a bit location (the type of edge/level is controlled by the INTTYPE2 register). The
user must make sure that the direction of port A/B/F is set to input and the corresponding bit
in the GPIO INTERRUPT ENABLE register is set to allow the interrupt.
All bits are cleared by a system reset.
The GPIOxINTTYPE2 registers controls the type of edge/level sensitive interrupt that can
occur on the bits in Ports A/B/F.
The interrupt is rising edge or high level sensitive if a “1” is written to the corresponding bit in
GPIOxINTTYPE2 and falling edge or low level sensitive if a “0” is written to the corresponding
bit in GPIOxINTTYPE2. The user must make sure that the direction of port A/B/F is set to
input and the corresponding bits in the GPIO Interrupt Enable register and GPIOxINTTYPE1
are set correctly in order for this register to have any effect. For edge sensitive interrupts the
GPIOxINTTYPE1 bit should set high and low for level sensitive interrupts.
All bits are cleared by a system reset.
30
14
29
13
28
12
RSVD
RSVD:
PxINTE:
GPIOAIntType2: 0x8084_0094 - Read/Write
GPIOBIntType2: 0x8084_00B0 - Read/Write
GPIOFIntType2: 0x8084_0050 - Read/Write
RSVD:
PxINTR:
27
11
26
10
25
9
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Determines which type of interrupt may occur.
Reserved. Unknown During Read.
Determines which type of edge or level sensitive interrupt
may occur.
24
8
RSVD
23
7
22
6
21
5
20
4
PxINTR
19
3
EP93xx User’s Guide
18
2
GPIO Interface
17
1
28-13
16
0
28