C8051F544-IM Silicon Laboratories Inc, C8051F544-IM Datasheet - Page 131

IC 8051 MCU 8K FLASH 32-QFN

C8051F544-IM

Manufacturer Part Number
C8051F544-IM
Description
IC 8051 MCU 8K FLASH 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F54xr
Datasheets

Specifications of C8051F544-IM

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
32-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F540DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1677-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F544-IM
Manufacturer:
Silicon Labs
Quantity:
135
Important Note: If the V
is selected as a reset source. Selecting the V
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
state is as follows:
1. Enable the V
2. If necessary, wait for the V
3. Select the V
See Figure 16.2 for V
monitor reset. See Table 6.4 for complete electrical characteristics of the V
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event. The
When programming the Flash in-system, the V
highest system reliability, the time the V
(e.g., setting the V
changing it back to the low threshold setting immediately after the Flash write operation).
Note: This delay should be omitted if software contains routines that erase or write Flash
memory.
output of the un-calibrated internal regulator could be below the high threshold setting of the VDD Monitor. If
this is the case and the V
reset (POR), the MCU will remain in reset until a POR occurs (i.e., V
POR will force the V
output of the internal regulator. The device will then exit reset and resume normal operation. It is for this reason
Silicon Labs strongly recommends that the V
value upon POR).
DD
DD
monitor as a reset source (PORSF bit in RSTSRC = 1).
DD
monitor (VDMEN bit in VDM0CN = 1).
Monitor to the high threshold setting just before the Flash write operation and then
DD
DD
DD
monitor timing; note that the power-on-reset delay is not incurred after a V
Monitor to the low threshold setting which is guaranteed to be below the un-calibrated
monitor is being turned on from a disabled state, it should be enabled before it
DD
DD
Monitor is set to the high threshold setting and if the MCU receives a non-power on
monitor to stabilize (see Table 6.4 for the V
DD
DD
Monitor is set to the high threshold setting should be minimized
monitor and configuring it as a reset source from a disabled
DD
DD
DD
Rev. 1.1
monitor as a reset source before it is enabled and stabi-
Monitor is always left in the low threshold setting (i.e., default
Monitor must be set to the high threshold setting. For the
DD
Monitor will keep the device in reset). A
DD
DD
monitor.
Monitor turn-on time).
C8051F54x
131
DD

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