C8051F544-IM Silicon Laboratories Inc, C8051F544-IM Datasheet - Page 97

• Manufacturer Part Number: C8051F544-IM
• Description: IC 8051 MCU 8K FLASH 32-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F54xr

Specifications of C8051F544-IM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 32-QFN
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F540DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1677-5

SFR Definition 12.2. SFRPAGE: SFR Page
SFR Address = 0xA7; SFR Page = All Pages
Bit
7:0
Name
Reset
Type
Bit
SFRPAGE[7:0]
Name
7
0
SFR Page Bits.
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
When enabled in the SFR Page Control Register (SFR0CN), the C8051 core will
automatically switch to the SFR Page that contains the SFRs of the correspond-
ing peripheral/function that caused the interrupt, and return to the previous SFR
page upon return from interrupt (unless SFR Stack was altered before a return-
ing from the interrupt). SFRPAGE is the top byte of the SFR Page Stack, and
push/pop events of this stack are caused by interrupts (and not by reading/writ-
ing to the SFRPAGE register)
6
0
5
0
Rev. 1.1
SFRPAGE[7:0]
4
0
R/W
Function
3
0
2
0
C8051F54x
1
0
0
0
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