C8051F544-IM Silicon Laboratories Inc, C8051F544-IM Datasheet - Page 29

• Manufacturer Part Number: C8051F544-IM
• Description: IC 8051 MCU 8K FLASH 32-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F54xr

Specifications of C8051F544-IM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 32-QFN
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F540DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1677-5

5. 12-Bit ADC (ADC0)
The ADC0 on the C8051F54x consists of an analog multiplexer (AMUX0) with 25/18 total input selections
and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, pro-
grammable window detector, programmable attenuation (1:2), and hardware accumulator. The ADC0 sub-
system has a special Burst Mode which can automatically enable ADC0, capture and accumulate
samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0, data
conversion modes, and window detector are all configurable under software control via the Special Func-
tion Registers shows in Figure 5.1. ADC0 inputs are single-ended and may be configured to measure
P0.0-P3.7, the Temperature Sensor output, V
ADC0 is selected as described in Section “6.2. Temperature Sensor” on page 60. ADC0 is enabled when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
P2.2-P2.7, P3.0 available
on 32-pin packages
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
Temp Sensor
GND
VDD
AMUX0
28-to-1
Figure 5.1. ADC0 Functional Block Diagram
ADC0GNH
ADC0MX
25 MHz Max
Burst Mode
Oscillator
Selectable
Gain
Conversion
ADC0GNL
SYSCLK
Start
DD
ADC0GNA
Burst Mode
, or GND with respect to GND. The voltage reference for
ADC0TK
Rev. 1.1
Logic
ADC0CF
ADC
12-Bit
SAR
ADC0GTH ADC0GTL
ADC0LTH
VDD
ADC0CN
ADC0LTL
Conversion
Start
C8051F54x
00
01
10
11
32
Accumulator
AD0WINT
Compare
AD0BUSY (W)
Timer 1 Overflow
CNVSTR Input
Timer 2 Overflow
Window
Logic
29