C8051F544-IM Silicon Laboratories Inc, C8051F544-IM Datasheet - Page 91

• Manufacturer Part Number: C8051F544-IM
• Description: IC 8051 MCU 8K FLASH 32-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F54xr

Specifications of C8051F544-IM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 32-QFN
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F540DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1677-5

C8051F54x
12.3. SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts. In this
example, the SFR Control register is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51
is executing in-line code that is writing values to SMBus Address Register (SFR “SMB0ADR”, located at
address 0xB9 on SFR Page 0x0F). The device is also using the SPI peripheral (SPI0) and the Programma-
ble Counter Array (PCA0) peripheral to generate a PWM output. The PCA is timing a critical control func-
tion in its interrupt service routine, and so its associated ISR is set to high priority. At this point, the SFR
page is set to access the SMB0ADR SFR (SFRPAGE = 0x0F). See Figure 12.2.
SFR Page
Stack SFR's
0x0F
SFRPAGE
(SMB0ADR)
SFRNEXT
SFRLAST
Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SMB0ADR
While CIP-51 executes in-line code (writing a value to SMB0ADR in this example), the SPI0 Interrupt
occurs. The CIP-51 vectors to the SPI0 ISR and pushes the current SFR Page value (SFR Page 0x0F) into
SFRNEXT in the SFR Page Stack. The SFR page needed to access SPI0’s SFRs is then automatically
placed in the SFRPAGE register (SFR Page 0x00). SFRPAGE is considered the “top” of the SFR Page
Stack. Software can now access the SPI0 SFRs. Software may switch to any SFR Page by writing a new
value to the SFRPAGE register at any time during the SPI0 ISR to access SFRs that are not on SFR Page
0x00. See Figure 12.3.
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