C8051F544-IM Silicon Laboratories Inc, C8051F544-IM Datasheet - Page 28

IC 8051 MCU 8K FLASH 32-QFN

C8051F544-IM

Manufacturer Part Number
C8051F544-IM
Description
IC 8051 MCU 8K FLASH 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F54xr
Datasheets

Specifications of C8051F544-IM

Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
32-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F540DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1677-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F544-IM
Manufacturer:
Silicon Labs
Quantity:
135
C8051F54x
28
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center ground
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Dimension
metal pad is to be 60 m minimum, all the way around the pad.
good solder paste release.
pad.
Components.
C1
C2
X1
E
Table 4.6. QFN-24 Landing Diagram Dimensions
 
3.90
3.90
0.20
Min
Figure 4.6. QFN-24 Landing Diagram
0.50 BSC
Max
4.00
4.00
0.30
Rev. 1.1
Dimension
X2
Y1
Y2
2.70
0.65
2.70
Min
Max
2.80
0.75
2.80

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