MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 110

MPU MX35 ARM11 400-MAPBGA

MCIMX357CJQ5C

Manufacturer Part Number
MCIMX357CJQ5C
Description
MPU MX35 ARM11 400-MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Datasheets

Specifications of MCIMX357CJQ5C

Core Processor
ARM11
Core Size
32-Bit
Speed
532MHz
Connectivity
1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
400-MAPBGA
Processor Series
i.MX357
Core
ARM1136JF-S
Data Bus Width
32 bit
Data Ram Size
128 KB
Interface Type
I2C, JTAG, UART
Maximum Clock Frequency
532 MHz
Number Of Timers
3
Operating Supply Voltage
1.33 V to 1.47 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX357CJQ5C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX357CJQ5CR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
pin. The modulated signal of the module is observed at this pin. It can be viewed as a clock signal whose
period and duty cycle can be varied with different settings of the PWM. The smallest period is two ipg_clk
periods with duty cycle of 50 percent.
4.9.20
This section details the electrical characteristics for the SJC module.
input timing.
Figure 90
110
depicts the SJC TRST timing, and
Outputs
Outputs
Outputs
SJC Electrical Specifications
(Input)
(Input)
Inputs
Figure 88
TCK
Data
Data
Data
Data
TCK
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
depicts the SJC boundary scan timing,
VIL
SJ3
Figure 88. Boundary Scan (JTAG) Timing Diagram
Figure 87. Test Clock Input Timing Diagram
VIH
SJ7
SJ6
SJ6
VIL
Table 73
VM
SJ2
lists the SJC timing parameters.
Output Data Valid
Output Data Valid
SJ1
SJ4
Input Data Valid
Figure 89
Figure 87
SJ3
SJ2
VM
VIH
depicts the SJC test access port,
SJ5
depicts the SJC test clock
Freescale Semiconductor

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