MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 35

• Manufacturer Part Number: MCIMX357CJQ5C
• Description: MPU MX35 ARM11 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX357
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, JTAG, UART
• Maximum Clock Frequency: 532 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.33 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.9.5.2
All WEIM output control signals may be asserted and deasserted by internal clocks related to the BCLK
rising edge or falling edge according to the corresponding assertion or negation control fields. The address
always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed
mode according to control register configuration. Output data begins related to BCLK rising edge except
in muxed mode where both rising and falling edge may be used according to control register configuration.
Freescale Semiconductor
1
2
NF10
NF11
NF12
NF13
NF14
NF15
NF16
NF17
NF5
NF6
NF7
NF8
NF9
The flash clock maximum frequency is 50 MHz.
Subject to DPLL jitter specification listed in
ID
NF_WP pulse width
NFALE setup time
NFALE hold time
Data setup time
Data hold time
Write cycle time
NFWE hold time
Ready to NFRE low
NFRE pulse width
READ cycle time
NFRE high hold time
Data setup on READ
Data hold on READ
Wireless External Interface Module (WEIM)
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.
Parameter
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Table 30. NFC Timing Parameters
Symbol
tREH
tDSR
tDHR
tALS
tALH
tWP
tWC
tWH
tDH
tRR
tRC
tDS
tRP
Table 27, "DPLL Specifications," on page
1.5T – 1.0 ns
2T – 5.5 ns
T = NFC Clock Cycle
T – 4.0 ns
T – 4.5 ns
T – 2.0 ns
T – 5.0 ns
NOTE
Min.
6T
0.5T – 4.0 ns
2T – 3.0 ns
T – 1.0 ns
T – 5.0 ns
Timing
N/A
N/A
1
(continued)
Max.
—
—
—
—
—
—
—
2
31.
NFC Clock
Min.
25.5
54.5
Example Timing for
180
26
28
25
44
11
9
0
T = 30 ns
29
57
25
≈
33 MHz
Max.
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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