MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 97

• Manufacturer Part Number: MCIMX357CJQ5C
• Description: MPU MX35 ARM11 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX357
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, JTAG, UART
• Maximum Clock Frequency: 532 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.33 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

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2
3
Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters
specified from the valid voltage threshold as listed below unless otherwise noted.
Freescale Semiconductor
MLB fall time
MLBCLK cycle time
MLBCLK low time
MLBCLK high time
MLBCLK pulse width variation
MLBSIG/MLBDAT input valid to
MLBCLK falling
MLBSIG/MLBDAT input hold
from MLBCLK low
MLBSIG/MLBDAT output high
impedance from MLBCLK low
Bus Hold Time
The MLB controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
MLBCLK Operating
MLBCLK cycle time
MLBCLK rise time
MLBCLK low time
MLB fall time
Frequency
Parameter
Parameter
1
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Table 59. MLB 256/512 Fs Timing Parameters (continued)
Symbol
Table 60. MLB Device 1024Fs Timing Parameters
Symbol
t
t
t
t
f
mckc
mckr
mckf
t
t
t
mckl
t
mck
t
t
t
t
t
dhmcf
mpwv
dsmcf
mcfdz
mckh
mdzh
mckc
mckf
mckl
45.056
Min
6.5
6.1
31.5
14.5
31.5
14.5
—
—
—
Min
30
14
30
14
—
—
—
—
1
0
0
4
49.152
20.3
35.5
16.5
36.5
16.5
Typ
Typ
7.7
7.3
—
—
81
40
37
17
38
17
—
—
—
—
—
—
49.2544
51.200
Max
Max
t
mckl
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
3
2
Units
MHz
Units
ns pp
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max: 1024 × Fs PLL unlocked
Max: 1024 × Fs at 48.1 kHz
Min: 1024 × Fs at 44.0 kHz
Typ: 1024 × Fs at 48.0 kHz
256 × Fs PLL unlocked
512 × Fs PLL unlocked
256 × Fs PLL unlocked
512 × Fs PLL unlocked
PLL unlocked
V
V
Comment
V
Comment
256 × Fs
512 × Fs
256 × Fs
512 × Fs
256 × Fs
512 × Fs
IL
IH
IH
Note
Note
TO V
TO V
—
TO V
—
—
—
2
3
IH
IL
IL
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