MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 77

• Manufacturer Part Number: MCIMX357CJQ5C
• Description: MPU MX35 ARM11 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX357
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, JTAG, UART
• Maximum Clock Frequency: 532 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.33 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Additionally, the IPU allows a programmable pause between two bursts. The pause is defined in the
HSP_CLK cycles. It allows the prevention of timing violation between two sequential bursts or two
accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
DISPB_PAR_RS
DISPB_PAR_RS
DISPB_PAR_RS
Freescale Semiconductor
DISPB_D#_CS
DISPB_D#_CS
DISPB_D#_CS
DISPB_BCLK
DISPB_DATA
DISPB_DATA
DISPB_DATA
DISPB_WR
DISPB_WR
DISPB_WR
DISPB_RD
DISPB_RD
DISPB_RD
Figure 54. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram
Single access mode (all control signals are not active for one display interface clock after each display access)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Burst access mode with sampling by separate burst clock (BCLK)
Burst access mode with sampling by CS signal
77