MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 112

• Manufacturer Part Number: MCIMX357CJQ5C
• Description: MPU MX35 ARM11 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX357
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, JTAG, UART
• Maximum Clock Frequency: 532 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.33 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

1
2
4.9.21
SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by
a clock that is twice the bit rate of the data signal.
Figure 91
SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK). for SPDIF in Tx mode.
112
SPDIFIN Skew: asynchronous inputs, no specs apply
SPDIFOUT output (Load = 50 pf)
SPDIFOUT1 output (Load = 30 pf)
Modulating Rx clock (SRCK) period
SRCK high period
SRCK low period
Modulating Tx clock (STCLK) period
STCLK high period
STCLK low period
SJ11 TCK low to TDO high impedance
SJ12 TRST assert time
SJ13 TRST set-up time to TCK low
• Skew
• Transition rising
• Transition falling
• Skew
• Transition rising
• Transition falling
On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
V
ID
M
= mid point voltage
shows SPDIF timing parameters, including the timing of the modulating Rx clock (SRCK) for
SPDIF Timing
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Parameters
Table 73. SJC Timing Parameters (continued)
Parameter
Table 74. SPDIF Timing Parameters
Symbol
stclkph
srckph
stclkpl
srckpl
stclkp
srckp
—
—
—
—
—
—
—
Timing Parameter Range
Min.
40.0
16.0
16.0
40.0
16.0
16.0
—
—
—
—
—
—
—
Min.
100
40
—
All Frequencies
Freescale Semiconductor
Max.
24.2
31.3
13.6
18.0
Max.
0.7
1.5
1.5
—
—
—
—
—
—
44
—
—
Units
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns