ATMEGA8U2-MU Atmel, ATMEGA8U2-MU Datasheet - Page 129

• Manufacturer Part Number: ATMEGA8U2-MU
• Description: MCU AVR 8K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

16.11 Register Description
16.11.1
7799D–AVR–11/10
TCCR1A – Timer/Counter1 Control Register A
Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f
•
•
•
The COMnA[1:0], COMnB[1:0], and COMnC[1:0] control the output compare pins (OCnA,
OCnB, and OCnC respectively) behavior. If one or both of the COMnA[1:0] bits are written to
one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If
one or both of the COMnB[1:0] bits are written to one, the OCnB output overrides the normal
port functionality of the I/O pin it is connected to. If one or both of the COMnC[1:0] bits are writ-
ten to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB
or OCnC pin must be set in order to enable the output driver.
When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx[1:0] bits is
dependent of the WGMn[3:0] bits setting.
when the WGMn[3:0] bits are set to a normal or a CTC mode (non-PWM).
and ICF n
Bit
(0x80)
Read/Write
Initial Value
Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
TCNTn
TCNTn
as TOP)
OCRnx
(clk
clk
clk
I/O
(FPWM)
I/O
Tn
/8)
(if used
COM1A1
R/W
7
0
COM1A0
TOP - 1
TOP - 1
R/W
6
0
Old OCRnx Value
COM1B1
R/W
5
0
COM1B0
TOP
TOP
R/W
Table 16-1
4
0
ATmega8U2/16U2/32U2
COM1C1
R/W
3
0
shows the COMnx[1:0] bit functionality
BOTTOM
TOP - 1
COM1C0
New OCRnx Value
R/W
2
0
clk_I/O
/8)
WGM11
BOTTOM + 1
R/W
1
0
TOP - 2
WGM10
R/W
0
0
TCCR1A
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