ATMEGA8U2-MU Atmel, ATMEGA8U2-MU Datasheet - Page 84

• Manufacturer Part Number: ATMEGA8U2-MU
• Description: MCU AVR 8K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

13. External Interrupts
13.1
13.2
13.2.1
7799D–AVR–11/10
Overview
Register Description
EICRA – External Interrupt Control Register A
The External Interrupts are triggered by the INT[7:0] pin or any of the PCINT[12:0] pins. Observe
that, if enabled, the interrupts will trigger even if the INT[7:0] or PCINT[12:0] pins are configured
as outputs. This feature provides a way of generating a software interrupt.
The Pin change interrupt PCI0 will trigger if any enabled PCINT[7:0] pin toggles. PCMSK0 Reg-
ister control which pins contribute to the pin change interrupts. The Pin change interrupt PCI1
will trigger if any enabled PCINT[12:8] pin toggles. PCMSK1 Register control which pins contrib-
ute to the pin change interrupts. Pin change interrupts on PCINT[12:0] are detected
asynchronously. This implies that these interrupts can be used for waking the part also from
sleep modes other than Idle mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the External Interrupt Control Registers – EICRA (INT[3:0])
and EICRB (INT[7:4]). When the external interrupt is enabled and is configured as level trig-
gered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or
rising edge interrupts on INT[7:4] requires the presence of an I/O clock, described in
Clock and Clock Options” on page
detected asynchronously. This implies that these interrupts can be used for waking the part also
from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle
mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3:0 Sense Control Bits
The External Interrupts 3:0 are activated by the external pins INT[3:0] if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
nously. Pulses on INT[3:0] pins wider than the minimum pulse width given in
Characteristics” on page 268
generate an interrupt. If low level interrupt is selected, the low level must be held until the com-
pletion of the currently executing instruction to generate an interrupt. If enabled, a level triggered
interrupt will generate an interrupt request as long as the pin is held low. When changing the
ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its
Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn
Bit
(0x69)
Read/Write
Initial Value
“System Clock and Clock Options” on page
ISC31
R/W
7
0
ISC30
R/W
6
0
will generate an interrupt. Shorter pulses are not guaranteed to
ISC21
R/W
26. Low level interrupts and the edge interrupt on INT[3:0] are
5
0
Table
ISC20
R/W
4
0
13-1. Edges on INT[3:0] are registered asynchro-
26.
ATmega8U2/16U2/32U2
ISC11
R/W
3
0
ISC10
R/W
2
0
ISC01
R/W
1
0
“External Interrupts
ISC00
R/W
0
0
EICRA
“System
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