ATMEGA8U2-MU Atmel, ATMEGA8U2-MU Datasheet - Page 260

• Manufacturer Part Number: ATMEGA8U2-MU
• Description: MCU AVR 8K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

25.9.1
7799D–AVR–11/10
Serial Programming Algorithm
When writing serial data to the ATmega8U2/16U2/32U2, data is clocked on the rising edge of
SCK.
When reading data from the ATmega8U2/16U2/32U2, data is clocked on the falling edge of
SCK. See
To program and verify the ATmega8U2/16U2/32U2 in the serial programming mode, the follow-
ing sequence is recommended (See four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
5. The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin PDI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
a time by supplying the 7 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the address
lines 15..8. Before issuing this command, make sure the instruction Load Extended
Address Byte has been used to define the MSB of the address. The extended address
byte is stored until the command is re-issued, i.e., the command needs only to be
issued for the first page, since the memory size is not larger than 64KWord. If polling
(
page. (See
write operation completes can result in incorrect programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling is not used, the user must
wait at least t
erased device, no 0xFFs in the data file(s) need to be programmed.
content at the selected address at serial output PDO. When reading the Flash memory,
use the instruction Load Extended Address Byte to define the upper address byte,
which is not included in the Read Program Memory instruction. The extended address
byte is stored until the command is re-issued, i.e., the command needs only to be
issued for the first page, since the memory size is not larger than 64KWord.
operation.
Set RESET to “1”.
Turn V
RDY/BSY
Figure 25-8
CC
) is not used, the user must wait at least t
power off.
Table
WD_EEPROM
for timing details.
25-15.) Accessing the serial programming interface before the Flash
CC
before issuing the next byte. (See
and GND while RESET and SCK are set to “0”. In some sys-
ATmega8U2/16U2/32U2
WD_FLASH
Table
before issuing the next
Table
25-15.) In a chip
25-16):
260