ATMEGA8U2-MU Atmel, ATMEGA8U2-MU Datasheet - Page 212

• Manufacturer Part Number: ATMEGA8U2-MU
• Description: MCU AVR 8K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

21.18.4
7799D–AVR–11/10
UDADDR – USB Device Address Register
• Bit 5 – EORSME: End Of Resume Interrupt Enable Bit
Writing this bit to one enables interrupt on EORSMI flag. An end of resume Upstream resume
interrupt will be generated only if the EORSME bit is set to one, the Global Interrupt Flag in
SREG is written to one, and the EORSMI bit is set.
• Bit 4 – WAKEUPE: Wake-up CPU Interrupt Enable Bit
Writing this bit to one enables interrupt on WAKEUPI flag. A wake-up interrupt will be generated
only if the WAKEUPE bit is set to one, the Global Interrupt Flag in SREG is written to one, and
the WAKEUPI bit is set.
• Bit 3 – EORSTE: End Of Reset Interrupt Enable Bit
Writing this bit to one enables interrupt on EORSTI flag. A USB reset interrupt will be generated
only if the EORSTE bit is set to one, the Global Interrupt Flag in SREG is written to one, and the
EORSTI bit is set.
• Bit 2 – SOFE: Start Of Frame Interrupt Enable Bit
Writing this bit to one enables interrupt on SOFI flag. A Start of Frame USB reset interrupt will be
generated only if the SOFE bit is set to one, the Global Interrupt Flag in SREG is written to one,
and the SOFI bit is set.
• Bit 1 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 0 – SUSPE: Suspend Interrupt Enable Bit
Writing this bit to one enables interrupt on SUSPI flag. A suspend interrupt will be generated
only if the SUSPE bit is set to one, the Global Interrupt Flag in SREG is written to one, and the
SUSPI bit is set.
• Bit 7 – ADDEN: Address Enable Bit
Writing this bit to one will enable the UADD[6:0] field as device address for the USB controller.
When this bit is set the USB device controller will be able to answer all requests on the USB that
refer to the UADD[6:0] USB bus address.
See
• Bits 6:0 – UADD[6:0]: USB Address Bits
These bits contain the USB device address, thatthe USB controller should answer on the USB
bus. This address should be enabled writing one to the ADDEN bit.
Bit
(0xE3)
Read/Write
Initial Value
“Address Setup” on page 199
ADDEN
R/W
7
0
R
6
0
R
5
0
for more details.
R
4
0
UADD[6:0]
ATmega8U2/16U2/32U2
R
3
0
R
2
0
R
1
0
R
0
0
UDADDR
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