ATMEGA8U2-MU Atmel, ATMEGA8U2-MU Datasheet - Page 217

• Manufacturer Part Number: ATMEGA8U2-MU
• Description: MCU AVR 8K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

21.18.13 UESTA0X – USB Endpoint Status 0 Register
7799D–AVR–11/10
• Bit 7 – CFGOK: Configuration Status Flag
This flag bit is set by hardware when the selected endpoint size parameter (EPSIZE) and num-
ber of banks (EPBK) are correct compared to the max FIFO capacity. This bit is updated when
the bit ALLOC is set, if the USB controller can not allocate the correct amount of memory for the
selected endpoint, this flag bit will be cleared.
If this bit is cleared, the user should reprogram the UECFG1X register with correct EPSIZE and
EPBK values.
• Bit 6 – OVERFI: Overflow Error Interrupt Flag
This flag is set when an overflow error occurs for an isochronous endpoint.This OVERFI flag can
generate a “USB endpoint interrupt” if FLERRE bit is set. Writing this bit to zero acknowledges
the interrupt source (USB clocks must be enabled before). Writing this bit to one has no effect.
See
• Bit 5 – UNDERFI: Underflow Error Interrupt Flag
This flag is set when an underflow error occurs for an isochronous endpoint.This UNDERFI flag
can generate a “USB endpoint interrupt” if FLERRE bit is set. Writing this bit to zero acknowl-
edges the interrupt source (USB clocks must be enabled before). Writing this bit to one has no
effect.
See
• Bit 4 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 3:2 – DTSEQ[1:0]: Data Toggle Sequencing Flag
These flags are set by hardware to indicate the PID data of the current bank as shown in
21-5.
For OUT transfer, this value indicates the last data toggle received on the current bank. For IN
transfer, it indicates the Toggle that will be used for the next packet to be sent. This is not rela-
tive to the current bank.
Table 21-5.
Bit
(0xEE)
Read/Write
Initial Value
“Isochronous mode” on page 207
“Isochronous mode” on page 207
DTSEQ1
CFGOK
0
0
1
1
R
7
0
DTSEQ[1:0] Bits Settings
OVERFI
R/W
6
0
UNDERFI
DTSEQ1
R/W
5
0
0
1
0
1
for more details.
for more details.
R
4
0
-
PID DATA
DATA0
DATA1
Reserved.
ATmega8U2/16U2/32U2
R
3
0
DTSEQ1:0
R
2
0
R
1
NBUSYBK1:0
0
R
0
0
UESTA0X
Table
217