ATMEGA8U2-MU Atmel, ATMEGA8U2-MU Datasheet - Page 210

• Manufacturer Part Number: ATMEGA8U2-MU
• Description: MCU AVR 8K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

21.18.2
7799D–AVR–11/10
UDINT – USB Device Interrupt Register
• Bits 7:3 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 2 – RSTCPU: USB Reset CPU Bit
Writing this bit to one allows the CPU controller to reset the CPU when a USB bus reset condi-
tion is detected. When this mode is activated, the next USB bus reset event allows to reset the
CPU and all peripherals except the USB controller. This mode allows to perform a software
reset, but keep the USB device attached to the bus.
This bit is reset when the USB controller is disabled or when writing this bit to zero by firmware.
Writing this bit to zero makes the CPU system reset independent from the USB bus reset event.
• Bit 1 – RMWKUP: Remote Wake-up Bit
Writing this bit to one allows the USB controller to generate an “upstream-resume” packet on the
USB bus. This bit is immediately cleared by hardware and can not be read back to one. Writing
this bit to zero has no effect.
See
• Bit 0 – DETACH: Detach Bit
Writing this bit to one (default value) disables the USB D+ internal pull-up. This makes the USB
device controller physically “detached” from the USB bus. Writing this bit to zero enables the D+
internal pull-up and physically connects the USB device controller to the USB bus. See
on page 200
• Bit 7 – Res: Reserved
This bit is reserved and should always read as zero.
• Bit 6 – UPRSMI: Upstream Resume Interrupt Flag
This flag is set by hardware when the USB controller has successfully sent the Upstream
Resume sequence (See description of
UPRSME is set, the UPRSMI flag can generate a “USB general interrupt”. Writing this bit to zero
acknowledges the interrupt source (USB clocks must be enabled before). Writing this bit to one
has no effect.
• Bit 5 – EORSMI: End Of Resume Interrupt Flag
This flag is set by hardware when the USB controller detects an End Of Resume sequence on
the USB initiated by the host. If the EORSME bit is set, the EORSMI flag can generate a “USB
general interrupt”. Writing this bit to zero acknowledges the interrupt source (USB clocks must
be enabled before). Writing this bit to one has no effect.
Bit
(0xE1)
Read/Write
Initial Value
“Remote Wake-up” on page 201
for more details.
R
7
0
-
UPRSMI
R/W
6
0
EORSMI
R/W
5
0
for more details.
“Bit 1 – RMWKUP: Remote Wake-up Bit” on page
WAKEUPI
R/W
4
0
EORSTI
ATmega8U2/16U2/32U2
R/W
3
0
SOFI
R/W
2
0
R
1
0
-
SUSPI
R/W
0
0
“Detach”
210). If
UDINT
210