ATMEGA8U2-MU Atmel, ATMEGA8U2-MU Datasheet - Page 40

• Manufacturer Part Number: ATMEGA8U2-MU
• Description: MCU AVR 8K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

8.11.6
7799D–AVR–11/10
PLLCSR – PLL Control and Status Register
Table 8-9.
• Bit 7:5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8U2/16U2/32U2 and always read as zero.
• Bit 4 – DIV5 PLL Input Prescaler (1:5)
• Bit 3 – DIV3 PLL Input Prescaler (1:3)
• Bit 2 – PINDIV PLL Input Prescaler (1:1, 1:2)
These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the
PLL from either a 8 or 16 MHz input.
When using a 8 MHz clock source, this bit must be set to 0 before enabling PLL (1:1).
When using a 16 MHz clock source, this bit must be set to 1 before enabling PLL (1:2).
• Bit 3:2 – Res: Reserved Bits
These bits are reserved and always read as zero.
Bit
0x29 (0x49)
Read/Write
Initial Value
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
R
7
–
0
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R
6
–
0
CLKPS1
R
5
–
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DIV5
R/W
4
0
CLKPS0
ATmega8U2/16U2/32U2
DIV3
R
3
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PINDIV
R
2
0
Clock Division Factor
PLLE
R/W
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PLOCK
128
256
16
32
64
1
2
4
8
R
0
0
PLLCSR
40