ATTINY26L-8PU Atmel, ATTINY26L-8PU Datasheet - Page 7

• Manufacturer Part Number: ATTINY26L-8PU
• Description: IC MCU AVR 2K 5V 8MHZ 20-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: 2-Wire/ISP/SM-Bus/SPI/UART/USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Controller Family/series: AVR Tiny
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATTINY26L-8PJ; ATTINY26L-8PJ

General Purpose
Register File
1477F–AVR–12/04
The AVR uses a Harvard architecture concept with separate memories and buses for
program and data memories. The program memory is accessed with a two stage
pipelining. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every
clock cycle. The program memory is In-System programmable Flash memory.
With the relative jump and relative call instructions, the whole address space is directly
accessed. All AVR instructions have a single 16-bit word format, meaning that every
program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 8-bit Stack Pointer SP is read/write accessible in the I/O
space. For programs written in C, the stack size must be declared in the linker file. Refer
to the C user guide for more information.
The 128 bytes data SRAM can be easily accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters, and other I/O functions. The memory spaces in the AVR
architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep-
arate Interrupt Vector in the Interrupt Vector table at the beginning of the program
memory. The different interrupts have priority in accordance with their Interrupt Vector
position. The lower the Interrupt Vector address, the higher the priority.
Figure 3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3. AVR CPU General Purpose Working Registers
Registers
Purpose
General
Working
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R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
R0
R1
R2
…
…
0
Addr.
$0D
$0E
$0F
$1A
$1B
$1C
$1D
$1E
$1F
$00
$01
$02
$10
$11
ATtiny26(L)
X-register High Byte
Y-register High Byte
Z-register High Byte
X-register Low Byte
Y-register Low Byte
Z-register Low Byte
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