ATTINY26L-8PU Atmel, ATTINY26L-8PU Datasheet - Page 98

• Manufacturer Part Number: ATTINY26L-8PU
• Description: IC MCU AVR 2K 5V 8MHZ 20-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: 2-Wire/ISP/SM-Bus/SPI/UART/USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Controller Family/series: AVR Tiny
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATTINY26L-8PJ; ATTINY26L-8PJ

Changing Channel or
Reference Selection
98
ATtiny26(L)
Figure 54. ADC Timing Diagram, Single Conversion
Figure 55. ADC Timing Diagram, Free Running Conversion
Table 43. ADC Conversion Time
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-
porary register to which the CPU has random access. This ensures that the channels
and reference selection only takes place at a safe point during the conversion. The
channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC
clock cycle before the conversion completes (ADIF in ADCSR is set). Note that the con-
version starts on the following rising ADC clock edge after ADSC is written. The user is
thus advised not to write new channel or reference selection values to ADMUX until one
ADC clock cycle after ADSC is written.
Condition
Extended conversion
Normal conversions
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
MUX and REFS
Update
Sample & Hold (Cycles from
Conversion
3
Complete
One Conversion
Start of Conversion)
Sample & Hold
4
11
5
12
13.5
1.5
6
13
7
One Conversion
8
Next Conversion
1
MSB of Result
LSB of Result
9
2
MUX and REFS
Update
10
Conversion
Complete
Time (Cycles)
3
11
Conversion
12
Sample & Hold
25
13
4
13
MSB of Result
LSB of Result
Next Conversion
1
Conversion
1477F–AVR–12/04
Time (µs)
125 - 500
65 - 260
2
MUX and REFS
Update
3