ATTINY26L-8PU Atmel, ATTINY26L-8PU Datasheet - Page 8

• Manufacturer Part Number: ATTINY26L-8PU
• Description: IC MCU AVR 2K 5V 8MHZ 20-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY26L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: 2-Wire/ISP/SM-Bus/SPI/UART/USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Controller Family/series: AVR Tiny
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK505 - ADAPTER KIT FOR 14PIN AVR MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATTINY26L-8PJ; ATTINY26L-8PJ

X-register, Y-register, and Z-
register
ALU – Arithmetic Logic
Unit
8
ATtiny26(L)
All of the register operating instructions in the instruction set have direct and single cycle
access to all registers. The only exceptions are the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and
the LDI instruction for load immediate constant data. These instructions apply to the
second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP,
AND, and OR, and all other operations between two registers or on a single register
apply to the entire Register File.
As shown in Figure 3, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being phys-
ically implemented as SRAM locations, this memory organization provides flexibility in
access of the registers, as the X-, Y-, and Z-registers can be set to index any register in
the file.
The registers R26..R31 have some added functions to their general purpose usage.
These registers are address pointers for indirect addressing of the Data Space. The
three indirect address registers X, Y, and Z are defined as:
Figure 4. X-, Y-, and Z-register
In the different addressing modes, these address registers have functions as fixed dis-
placement, automatic increment and decrement (see the descriptions for the different
instructions).
The high-performance AVR ALU operates in direct connection with all 32 general pur-
pose working registers. Within a single clock cycle, ALU operations between registers in
the Register File are executed. The ALU operations are divided into three main catego-
ries – Arithmetic, Logical, and Bit-functions.
X-register
Y-register
Z-register
15
7
R29 ($1D)
15
7
R27 ($1B)
15
7
R31 ($1F)
0
0
0
7
R28 ($1C)
7
R26 ($1A)
7
R30 ($1E)
1477F–AVR–12/04
0
0
0
0
0
0