AT91SAM7S32B-AU-999 Atmel, AT91SAM7S32B-AU-999 Datasheet - Page 304

IC MCU ARM7 32KB FLASH 48LQFP

AT91SAM7S32B-AU-999

Manufacturer Part Number
AT91SAM7S32B-AU-999
Description
IC MCU ARM7 32KB FLASH 48LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM7S32B-AU-999

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, JTAG, SPI, USART
Maximum Clock Frequency
55 MHz
Number Of Programmable I/os
21
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S32B-AU-999
Manufacturer:
Atmel
Quantity:
10 000
304
AT91SAM7S Series Preliminary
Figure 29-18. TWI Read Operation with Multiple Data Bytes with or without Internal Address
No
Read Receive Holding register (TWI_RHR)
Read Receive Holding register (TWI_RHR)
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Internal address size (if IADR used)
Set the Master Mode register:
Read ==> bit MREAD = 1
Internal address size = 0?
Set the Control register:
- Device slave address
- Transfer direction bit
Read Status register
Read Status register
Read status register
(Needed only once)
TWI_CR = MSEN
TWI_CR = START
Yes
TWI_CR = STOP
Start the transfer
Last data to read
Stop the transfer
- Master enable
TXCOMP = 1?
Set TWI clock
RXRDY = 1?
Yes
Yes
Yes
RXRDY = 1?
Yes
but one?
BEGIN
END
No
No
No
Set the internal address
TWI_IADR = address
6175K–ATARM–30-Aug-10

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