AT91SAM7S32B-AU-999 Atmel, AT91SAM7S32B-AU-999 Datasheet - Page 614

• Manufacturer Part Number: AT91SAM7S32B-AU-999
• Description: IC MCU ARM7 32KB FLASH 48LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S32B-AU-999

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, JTAG, SPI, USART
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 21
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7S-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

40.6.2.6
40.6.2.7
40.6.2.8
40.6.2.9
40.6.2.10
614
AT91SAM7S Series Preliminary
ADC: GOVRE Bit is not Set when Reading CDR
ADC: GOVRE Bit is not Set when Disabling a Channel
ADC: OVRE Flag Behavior
ADC: EOC Set although Channel Disabled
ADC: Spurious Clear of EOC Flag
None
When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on
channel “x” with the following conditions:
GOVRE should be set but is not.
None
When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x]
and DRDY being already active, GOVRE does not rise.
Note:
None
When the OVRE flag (on channel i) has been set but the related EOC status (of channel i) has
been cleared (by a read of CDRi or LCDR), reading the Status register at the same instant as an
end of conversion (causing the set of EOC status on channel i), does not lead to a reset of the
OVRE flag (on channel i) as expected.
None
If a channel is disabled while a conversion is running and if a read of CDR is performed at the
same time as an end of conversion of any channel occurs, the EOC of the channel with the con-
version running may rise (whereas it has been disabled).
Do not take into account the EOC of a disabled channel
If “x” and “y” are two successively converted channels and “z” is yet another enabled channel
(“z” being neither “x” nor “y”), reading CDR on channel “z” at the same instant as an end of con-
version on channel “y” automatically clears EOC[x] instead of EOC[z].
1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun
2. GOVRE is inactive but DRDY is active, does correspond to a new general overrun con-
• EOC[x] already active,
• DRDY already active,
• GOVRE inactive,
• previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
condition but the GOVRE flag is not reset.
dition but the GOVRE flag is not set.
OVRE[x] rises as expected.
6175K–ATARM–30-Aug-10