AT89S8253-24PU Atmel, AT89S8253-24PU Datasheet - Page 10

• Manufacturer Part Number: AT89S8253-24PU
• Description: IC 8051 MCU FLASH 12K 40DIP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S8253-24PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Cpu Family: 89S
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 256Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

6.1
Table 6-1.
Figure 6-1.
10
EECON Address = 96H
Not Bit Addressable
Symbol
EELD
EEMWE
EEMEN
DPS
RDY/BSY
WRTINH
Bit
Memory Control Register
AT89S8253
Function
EEPROM data memory load enable bit. Used to implement Page Mode Write. A MOVX instruction writing into the data
EEPROM will not initiate the programming cycle if this bit is set, rather it will just load data into the volatile data buffer of
the data EEPROM memory. Before the last MOVX, reset this bit and the data EEPROM will program all the bytes
previously loaded on the same page of the address given by the last MOVX instruction.
EEPROM data memory write enable bit. Set this bit to 1 before initiating byte write to on-chip EEPROM with the MOVX
instruction. User software should set this bit to 0 after EEPROM write is completed.
Internal EEPROM access enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM
instead of external data memory if the address used is less than 2K. When EEMEN = 0 or the address used is ≥ 2K,
MOVX with DPTR accesses external data memory.
Data pointer register select. DPS = 0 selects the first bank of data pointer register, DP0, and DPS = 1 selects the
second bank, DP1.
RDY/BSY (Ready/Busy) flag for the data EEPROM memory. This is a read-only bit which is cleared by hardware during
the programming cycle of the on-chip EEPROM. It is also set by hardware when the programming is completed. Note
that RDY/BSY will be cleared long after the completion of the MOVX instruction which has initiated the programming
cycle.
WRTINH (Write Inhibit) is a READ-ONLY bit which is cleared by hardware when V
of the on-chip EEPROM to be executed. When this bit is cleared, an ongoing programming cycle will be aborted or a
new programming cycle will not start.
EECON – Data EEPROM Control Register
Data EEPROM Write Sequence
MOVX DATA
RDY/BSY
–
7
EEMWE
EEMEN
EELD
In addition, during EEPROM programming, an attempted read from the EEPROM will fetch the
byte being written with the MSB complemented. Once the write cycle is completed, true data are
valid at all bit locations.
The EECON register contains control bits for the 2K bytes of on-chip data EEPROM. It also con-
tains the control bit for the dual data pointer.
–
6
EELD
5
0
1
EEMWE
4
2
3
EEMEN
3
30
DPS
2
cc
31
is too low for the programming cycle
Reset Value = XX00 0011B
RDY/BSY
~
4 ms
1
WRTINH
3286P–MICRO–3/10
0