AT89S8253-24PU Atmel, AT89S8253-24PU Datasheet - Page 9

• Manufacturer Part Number: AT89S8253-24PU
• Description: IC 8051 MCU FLASH 12K 40DIP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S8253-24PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Cpu Family: 89S
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 256Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

5.5
5.6
6. Data Memory – EEPROM and RAM
3286P–MICRO–3/10
Dual Data Pointer Registers
Power Off Flag
To facilitate accessing both internal EEPROM and external data memory, two banks of 16-bit
Data Pointer Registers are provided: DP0 at SFR address locations 82H - 83H and DP1 at 84H
- 85H. Bit DPS = 0 in SFR EECON selects DP0 and DPS = 1 selects DP1. The user should
ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data
Pointer Register.
The Power Off Flag (POF), located at bit_4 (PCON.4) in the PCON SFR. POF, is set to “1” dur-
ing power up. It can be set and reset under software control and is not affected by RESET.
The AT89S8253 implements 2K bytes of on-chip EEPROM for data storage and 256 bytes of
RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers.
That means the upper 128 bytes have the same addresses as the SFR space but are physically
separate from SFR space. When an instruction accesses an internal location above address
7FH, the address mode used in the instruction specifies whether the CPU accesses the upper
128 bytes of RAM or the SFR space. Instructions that use direct addressing access the SFR
space.For example, the following direct addressing instruction accesses the SFR at location
0A0H (which is P2).
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the
following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at
address 0A0H, rather than P2 (whose address is 0A0H).
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data
RAM are available as stack space.
The on-chip EEPROM data memory is selected by setting the EEMEN bit in the EECON register
at SFR address location 96H. The EEPROM address range is from 000H to 7FFH. MOVX
instructions are used to access the EEPROM. To access off-chip data memory with the MOVX
instructions, the EEMEN bit needs to be set to “0”.
During program execution mode (using the MOVX instruction) there is an auto-erase capability
at the byte level. This means that the user can update or modify a single EEPROM byte location
in real-time without affecting any other bytes.
The EEMWE bit in the EECON register needs to be set to “1” before any byte location in the
EEPROM can be written. User software should reset EEMWE bit to “0” if no further EEPROM
write is required. EEPROM write cycles in the serial programming mode are self-timed and typi-
cally take 4 ms. The progress of EEPROM write can be monitored by reading the RDY/BSY bit
(read-only) in SFR EECON. RDY/BSY = 0 means programming is still in progress and RDY/BSY
= 1 means an EEPROM write cycle is completed and another write cycle can be initiated. Bit
EELD in EECON controls whether the next MOVX instruction will only load the write buffer of the
EEPROM or will actually start the programming cycle. By setting EELD, only load will occur.
Before the last MOVX in a given page of 32 bytes, EELD should be cleared so that after the last
MOVX the entire page will be programmed at the same time. This way, 32 bytes will only require
4 ms of programming time instead of 128 ms required in single byte programming.
MOV 0A0H, #data
MOV @R0, #data
AT89S8253
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