AT89S8253-24PU Atmel, AT89S8253-24PU Datasheet - Page 37

• Manufacturer Part Number: AT89S8253-24PU
• Description: IC 8051 MCU FLASH 12K 40DIP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S8253-24PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Cpu Family: 89S
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 256Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

20. Programming the Flash and EEPROM
3286P–MICRO–3/10
Atmel’s AT89S8253 Flash microcontroller offers 12K bytes of In-System reprogrammable Flash
code memory and 2K bytes of EEPROM data memory.
The AT89S8253 is normally shipped with the on-chip Flash code and EEPROM data memory
arrays in the erased state (i.e. contents = FFH) and ready to be programmed. This device sup-
ports a parallel programming mode and a serial programming mode. The serial programming
mode provides a convenient way to reprogram the AT89S8253 inside the user’s system. The
parallel programming mode is compatible with conventional third-party Flash or EPROM
programmers.
The code and data memory arrays are mapped via separate address spaces in the parallel and
serial programming modes: 0000H to 2FFFH for code memory and 000H to 7FFH for data
memory.
The code and data memory arrays in the AT89S8253 are programmed byte-by-byte or by page
in either programming mode. To reprogram any non-blank byte in the parallel or serial mode, the
user needs to invoke the Chip Erase operation first to erase both arrays since there is no built-in
auto-erase capability.
Parallel Programming Algorithm: To program and verify the AT89S8253 in the parallel pro-
gramming mode, the following sequence is recommended (see
1. Power-up sequence:
2. Set PSEN pin to “L”
3. Raise EA/VPP to 12V to enable Flash programming, erase or verification. Enable the
4. Apply the appropriate combination of “H” or “L” logic levels to pins P3.3, P3.4, P3.5,
5. Apply the desired byte address to pins P1.0 to P1.7 and P2.0 to P2.5.
6. Pulse ALE/PROG once to load a byte in the code memory array, the data memory
7. Repeat steps 5 and 6, changing the address and data for up to 64 bytes in the code
8. After the last byte of the current page has been loaded, wait for 5 ms or monitor the
9. To verify the last byte of the page just programmed, bring pin P3.4 to “L” and read the
a. Apply power between V
b. Set RST pin to “H”.
c. Apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait for at least 10 ms.
a. ALE pin to “H”
b. EA pin to “H” and all other pins to “H”.
P3.0 pull-up (10 KΩ typical) for RDY/BSY operation.
P3.6, P3.7 to select one of the programming operations shown in the Flash Program-
ming Modes table.
a. Apply data to pins P0.0 to P0.7 for write code operation.
array, or the lock bits.
memory page or 32 bytes in the data memory (EEPROM) page. When loading a page
with individual bytes, the interval between consecutive byte loads should be no longer
than 150 µs. Otherwise the device internally times out and assumes that the page load
sequence is completed, rejecting any further loads before the page programming
sequence has finished. This timing restriction also applies to Page Write of the 64-byte
User Row.
RDY/BUSY pin until it transitions high. The page write cycle is self-timed and typically
takes less than 5 ms.
programmed data at pins P0.0 to P0.7.
CC
and GND pins.
Figure
26-1):
AT89S8253
37