AT89S8253-24PU Atmel, AT89S8253-24PU Datasheet - Page 36

• Manufacturer Part Number: AT89S8253-24PU
• Description: IC 8051 MCU FLASH 12K 40DIP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S8253-24PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Cpu Family: 89S
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: SPI/UART
• Total Internal Ram Size: 256Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

18. Power-down Mode
19. Program Memory Lock Bits
36
AT89S8253
Table 17-1.
In the power-down mode, the oscillator is stopped and the instruction that invokes power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the power-down mode is terminated. Exit from power-down can be initiated either by
a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not
change the on-chip RAM. The reset should not be activated before V
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
To exit power-down via an interrupt, external interrupt pin P3.2 or P3.3 must be kept low for at
least the specified required crystal oscillator start up time. Afterwards, the interrupt service rou-
tine starts at the rising edge of the external interrupt pin if the SFR bit AUXR.1 is set. If AUXR.1
is reset (cleared), execution starts after a self-timed interval of 2 ms (nominal) from the falling
edge of the external interrupt pin. The user should not attempt to enter (or re-enter) the power-
down mode for a minimum of 4 µs until after one of the following conditions has occurred: Start
of code execution (after any type of reset), or Exit from power-down mode.
The AT89S8253 has three lock bits that can be left unprogrammed (U) or can be programmed
(P) to obtain the additional features listed in
logic level at the EA pin is sampled and latched during reset. If the device is powered up without
a reset, the latch initializes to a random value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level at that pin in order for the device to
function properly. Once programmed, the lock bits can only be unprogrammed with the Chip
Erase operation in either the parallel or serial modes.
Table 19-1.
Note:
Mode
Idle
Idle
Power-down
Power-down
1
2
3
4
Program Lock Bits
1. U = Unprogrammed; P = Programmed
LB1
U
P
P
P
Status of External Pins During Idle and Power-down Modes
Lock Bit Protection Modes
Program Memory
Internal
External
Internal
External
LB2
U
U
P
P
LB3
U
U
U
P
Protection Type
No internal memory lock feature.
MOVC instructions executed from external program memory are
disabled from fetching code bytes from internal memory. EA is sampled
and latched on reset and further programming of the Flash memory
(parallel or serial mode) is disabled.
Same as Mode 2, but parallel or serial verify are also disabled.
Same as Mode 3, but external execution is also disabled.
ALE
1
1
0
0
(1)
Table
PSEN
1
1
0
0
19-1. When lock bit 1 is programmed, the
PORT0
Float
Float
Data
Data
PORT1
Data
Data
Data
Data
CC
is restored to its normal
Address
PORT2
Data
Data
Data
3286P–MICRO–3/10
PORT3
Data
Data
Data
Data