ATMEGA3250-16AUR Atmel, ATMEGA3250-16AUR Datasheet - Page 144

• Manufacturer Part Number: ATMEGA3250-16AUR
• Description: MCU AVR 32K FLASH 16MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3250-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2570M–AVR–04/11
• Bit 5:4 – COM2A1:0: Compare Match Output Mode A
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be
set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM21:0 bit setting.
are set to a normal or CTC mode (non-PWM).
Table 17-3.
Table 17-4
mode.
Table 17-4.
Note:
Table 17-5
rect PWM mode.
Table 17-5.
Note:
COM2A1
COM2A1
COM2A1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at BOTTOM. See
page 136
pare match is ignored, but the set or clear is done at TOP. See
page 138
shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor-
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
COM2A0
COM2A0
COM2A0
0
1
0
1
0
1
0
1
0
1
0
1
for more details.
for more details.
Table 17-3
Description
Normal port operation, OC2A disconnected.
Reserved
Clear OC2A on compare match, set OC2A at BOTTOM,
(non-inverting mode).
Set OC2A on compare match, clear OC2A at BOTTOM,
(inverting mode).
Description
Normal port operation, OC2A disconnected.
Reserved
Clear OC2A on compare match when up-counting. Set OC2A on
compare match when counting down.
Set OC2A on compare match when up-counting. Clear OC2A on
compare match when counting down.
Description
Normal port operation, OC2A disconnected.
Toggle OC2A on compare match.
Clear OC2A on compare match.
Set OC2A on compare match.
shows the COM2A1:0 bit functionality when the WGM21:0 bits
ATmega325/3250/645/6450
(1)
(1)
“Phase Correct PWM Mode” on
“Fast PWM Mode” on
144